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Pei Te Ouyang

from San Jose, CA
Age ~64
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Also known as:
Pei Owyang
Phone and address:
1251 Alderbrook Ln, San Jose, CA 95129
(408) 446-1449
Related to:
Clare R Ouyang, 35Karen H OuyangChiayi Y Ouy, 63
Connected to:
Alexander U Ouyang, 35Chenguang Ouyang, 44Christina Ouyang, 36Elaine Ouyang, 36Flora Ouyang, 90Hong Ouyang, 63Howard Ouyang, 41Huan Ouyang, 66Lulu Ouyang, 31Pengbo Ouyang, 35

Pei Ouyang Phones & Addresses

  • 1251 Alderbrook Ln, San Jose, CA 95129 (408) 446-1449
  • San Francisco, CA
  • Cupertino, CA
  • Mountain View, CA
  • Brooklyn, NY
  • 1251 Alderbrook Ln, San Jose, CA 95129 (619) 690-3902

Work

Company: Google Sep 2010 Position: Engineer

Education

Degree: Ph.D. School / High School: New York University 1988 to 1992 Specialities: Computer Science

Languages

English • Mandarin

Ranks

Certificate: Machine Learning

Interests

Cooking • Investing • Outdoors • Electronics • Home Improvement • Music • Sports • Travel • Movies • Collecting

Industries

Computer Software

Resumes

Resumes

Pei Ouyang Photo 1

Engineer At Google

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Location:
1251 Alderbrook Ln, San Jose, CA 95129
Industry:
Computer Software
Work:
Google since Sep 2010
Engineer
Yahoo Mar 2007 - Sep 2010
Engineer
Synopsys Feb 2005 - Mar 2007
Engineer
Cadence Design, Inc. 2004 - 2005
Engineer
Attest Design Automation 2002 - 2004
Engineer
Education:
New York University 1988 - 1992
Ph.D., Computer Science New York University 1986 - 1988
M.S., Computer Science National Taiwan University 1982 - 1984
M.S., Electrical Engineering National Taiwan University 1978 - 1982
B.S., Electrical Engineering Chiayi High School, 嘉義高中 1975 - 1978
大業國中 1972 - 1975
崇文國小 1966 - 1972
Interests:
Cooking
Investing
Outdoors
Electronics
Home Improvement
Music
Sports
Travel
Movies
Collecting
Languages:
English
Mandarin
Certifications:
Machine Learning

Publications

Us Patents

Race Condition Detection And Expression

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US Patent:
7017129, Mar 21, 2006
Filed:
Feb 3, 2003
Appl. No.:
10/357921
Inventors:
Pei Ouyang - San Jose CA, US
Assignee:
Verisity Design, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).

Race Condition Detection And Expression

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US Patent:
7243319, Jul 10, 2007
Filed:
Nov 15, 2004
Appl. No.:
10/990121
Inventors:
Pei Ouyang - San Jose CA, US
Assignee:
Cadence Design (Israel) II Ltd. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4
Abstract:
A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).

Race Condition Detection And Expression

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US Patent:
6536019, Mar 18, 2003
Filed:
Sep 28, 2000
Appl. No.:
09/672382
Inventors:
Pei Ouyang - San Jose CA
Assignee:
Verisity Design, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
716 4, 716 6
Abstract:
A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).
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Pei Te Ouyang from San Jose, CA, age ~64 Get Report