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Pei Ping Lin

from Round Rock, TX
Age ~41
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Also known as:
Pei P Lin, Penny P Lin, Peiping Lin, Ping Pei Lin, Chia Pei Lin, Ping Lin Pei, Lin Chia Peichia, Lin Pei, Lin Peiping
Related to:
You Jhen Chen, 64Flo A Myers, 89Penny LinLu Chen, 38Mary C Abille, 65William F Myers, 94Rex M AbilleMaria M Abille, 52Hsiu Yuan Chen, 50Ping Lin Jui, 43Amy H Chen, 63Rex Abille, 60Diana Lin, 36Kevin A Lopez, 45Dongmei Mei Lin, 54Xiaohong H Chen, 61M ChenJui Ping Lin, 43
Connected to:
Abbie Lin, 37Adie S Lin, 80Adora A Lin, 44Agnes C Lin, 46Aileen Lin, 55Alston C Lin, 27Angela L Lin, 75Angelo C Lin, 60Anne Lin, 45Anya Y Lin, 47

Pei Lin Phones & Addresses

  • Round Rock, TX
  • Fremont, CA
  • Union City, CA
  • Discovery Bay, CA
  • San Jose, CA
  • Oklahoma City, OK

Professional Records

Medicine Doctors

Pei Lin Photo 1

Pei S. Lin

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Specialties:
Otolaryngology
Work:
Pei Lin MD ENT
2864 State Rte 27 STE A, North Brunswick, NJ 08902
(732) 966-1703 (phone), (732) 297-1894 (fax)

Pei Lin MD ENT
3624 John F Kennedy Blvd, Jersey City, NJ 07307
(201) 577-4509 (phone), (201) 510-0350 (fax)
Education:
Medical School
Coll of Med Natl Taiwan Univ, Taipei, Taiwan (244 02 Eff 1/1971)
Graduated: 1967
Procedures:
Allergy Testing
Hearing Evaluation
Inner Ear Tests
Myringotomy and Tympanotomy
Sinus Surgery
Skull/Facial Bone Fractures and Dislocations
Tympanoplasty
Conditions:
Acute Otitis Externa
Acute Pharyngitis
Acute Sinusitis
Labyrinthitis
Otitis Media
Languages:
English
Description:
Dr. Lin graduated from the Coll of Med Natl Taiwan Univ, Taipei, Taiwan (244 02 Eff 1/1971) in 1967. He works in Jersey City, NJ and 1 other location and specializes in Otolaryngology.
Pei Lin Photo 2

Pei Lin

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Specialties:
Pathology
Anatomic Pathology & Clinical Pathology
Hematology
Hematology
Education:
Nanjing University Medical College (1982)
Pei Lin Photo 3

Pei Shiu Lin

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Specialties:
Otolaryngology
Otolaryngic Allergy
Pediatric Otolaryngology
Education:
Taipei Medical University (1967)

Resumes

Resumes

Pei Lin Photo 4

Experienced Scientist/Engineer

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Position:
Supervisor at Lawrence Berkeley National Laboratory
Location:
Sunnyvale, California
Industry:
Pharmaceuticals
Work:
Lawrence Berkeley National Laboratory - Walnut creek since Sep 2011
Supervisor
The Scripps Research Institute 2009 - Jul 2011
Scientific Associate, 2011 Nobel Prize in Medicine Winner Dr. Bruce Beutler lab
Medimmune 2006 - 2008
Scientist/Engineer
XDx.Inc 2004 - 2006
Lab Automation Associate II
The Scripps Research Institute 2002 - 2003
Research Assistant, 2011 Nobel Prize in Medicine Winner Dr. Bruce Beutler lab
Pei Lin Photo 5

Modeling Engineer

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Industry:
Semiconductors
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Pei Lin

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Pei Lin Photo 7

Pei Lin

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Pei Lin Photo 8

Pei Lin

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Pei Lin Photo 9

Pei Lin

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Work:
Georgetown University
Student
Pei Lin Photo 10

Pei Lin

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Pei Lin Photo 11

Pei Lin

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Pei Ying Lin
President
Edesignershop, Inc
48511 Warm Spg Blvd, Fremont, CA 94539
Pei S. Lin
Medical Doctor
Ent and Allergy Associates Llp
Medical Doctor's Office
Pei Lian Lin
President
SINO-AMERICAN INTERCULTURAL ECONOMIC LINK CENTER
110 Malcolm Dr, Richmond, CA 94801

Publications

Us Patents

Estimation Of Pin-To-Pin Timing For Compiled Blocks

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US Patent:
55965059, Jan 21, 1997
Filed:
Jul 23, 1993
Appl. No.:
8/096130
Inventors:
Russell L. Steinweg - Santa Clara CA
Michael A. Zampaglione - San Jose CA
Pei H. Lin - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
364490
Abstract:
A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.

Automatic Optimization Of A Compiled Memory Structure Based On User Selected Criteria

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US Patent:
56257970, Apr 29, 1997
Filed:
Nov 3, 1993
Appl. No.:
8/148420
Inventors:
Thomas V. Ferry - San Jose CA
Russell L. Steinweg - Santa Clara CA
Michael A. Zampaglione - San Jose CA
Pei H. Lin - San Jose CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1202
US Classification:
39549704
Abstract:
A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.

Method For Verifying Circuit Layout Design

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US Patent:
54503310, Sep 12, 1995
Filed:
Jan 24, 1992
Appl. No.:
7/825490
Inventors:
Pei Lin - San Jose CA
Herve G. Duprez - Campbell CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1560
US Classification:
364490
Abstract:
The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e. g. , minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.
Control profile
Pei Ping Lin from Round Rock, TX, age ~41 Get Report