Pazhani S Pillai

8090801, Jan 3, 2012

Jan 29, 2004

10/767182

Pazhani Pillai - Billerica MA, US
Daniel R. Cassiday - Topsfield MA, US
Don M. Morrier - Hudson NH, US
John R. Feehrer - Westford MA, US

Oracle America, Inc. - Redwood City CA

G06F 15/16
G06F 15/173
G06F 9/46

709219, 709217, 709242, 709249, 709250, 718108

A system, methods and apparatus perform remote access commands between nodes and allow preemption of context resources in an architecture such as Infiniband. The system detects an original request in a request queue for a data access task to access data from a first node to a second node and issues a first request from a first node to a second node. The first request requests the data access task be performed between the first node and the second node. The system receives, at the first node, a first response from the second node that partially completes the data access task. The system issues at least one subsidiary request from the first node to the second node to further complete the data access task between the first node and the second node. The subsidiary request(s) are based on an amount of partial completion of the data access task between the first node and the second node. The system receives, from the second node in response to the subsidiary request, at least one corresponding subsidiary response that further completes the data access task between the first node and the second node.

20030070058, Apr 10, 2003

Oct 9, 2001

09/973279

Boris Ostrovsky - Sudbury MA, US
Daniel Cassiday - Topsfield MA, US
John Feehrer - Westford MA, US
David Wood - Madison WI, US
Pazhani Pillai - Billerica MA, US
Christopher Jackson - Westford MA, US
Mark Hill - Madison WI, US

G06F012/10

711/209000, 711/207000, 711/133000, 711/144000

A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

20200202605, Jun 25, 2020

Dec 19, 2018

16/226103

- Santa Clara CA, US
Pazhani Pillai - Boxborough MA, US

Advanced Micro Devices, Inc. - Santa Clara CA

G06T 15/00
G06T 1/20
G06T 17/20
G06T 7/40
G06T 7/90
G06K 9/62

A technique for determining the centroid for fragments generated using variable rate shading is provided. Because the barycentric interpolation used to determine texture coordinates for pixels is based on the premise that the point being interpolated is within the triangle, centroids that are outside of the triangle can produce undesirable visual artifacts. Another concern, however, is that the further the centroid is from the center of a pixel, the less accurate quad-based pixel derivatives become for attributes of that pixel. To address these concerns, the position of the sample that is both covered by the triangle and the closest to the center of the pixel, out of all covered samples of the pixel, is used as the centroid for a partially covered pixel. For a fully covered pixel (all samples in a pixel are covered by a triangle), the center of that pixel is used as the centroid.

20200175642, Jun 4, 2020

Dec 3, 2018

16/208073

- Santa Clara CA, US
Pazhani Pillai - Tewksbury MA, US

G06T 1/20
G06T 15/80
G06T 1/60
G06T 7/507

Systems, apparatuses, and methods for implementing pixel wait synchronization techniques are disclosed. A system includes a host processor and a graphics processor which includes at least one graphics pipeline. During execution of a graphics application, the host processor determines that a second draw call is dependent on a first draw call. The host processor issues a wait sync event prior to issuing the second draw call to the graphics pipeline responsive to determining that the first draw call is still in-flight in the graphics pipeline. After the second draw call is issued to the graphics pipeline, the second draw call is processed by one or more stages of the graphics pipeline while the first draw call is still in-flight. The graphics pipeline stalls the second draw call at a given intermediate stage until a corresponding event counter equals a value specified by the wait sync event.