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Paul J Sulva

from Jericho, VT
Age ~55
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Related to:
Peter M SantulliAnna M Cummings, 65Joseph C Miller, 71Patricia SulvaAugust Wittorp, 36
Connected to:
Michael Sulva, 64Vladimir V Sulyagin, 66Tracy A Sulyma, 63Thomas J Sulyok, 80Rachael R Sulz, 48Earl Sulzbacher, 83Evan T Sulzbach, 32Frederica M Sulzbacher, 72Gina M Sulzbacher, 57Idamay F Sulzbach, 36

Paul Sulva Phones & Addresses

  • 22 Griswold St, Jericho, VT 05465 (802) 578-4266
  • South Burlington, VT
  • 22 Griswold St, Jericho, VT 05465

Work

Company: Globalfoundries Jul 2015 Position: Asic methodology development engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Purdue University 1987 to 1991 Specialities: Electronics Engineering

Skills

Asic • Vlsi • Physical Design • Eda • Methodology • Cmos • Physical Verification • Integration • Semiconductors • Drc • Circuit Design • Cadence Virtuoso • Testing • Microprocessors • Modelsim • Ic • Perl • Debugging • Tcl • Very Large Scale Integration • Application Specific Integrated Circuits

Languages

English

Interests

Education

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Paul Sulva Photo 1

Asic Methodology Development Engineer

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Location:
Burlington, VT
Industry:
Electrical/Electronic Manufacturing
Work:
Globalfoundries
Asic Methodology Development Engineer
Ibm Oct 2006 - Jun 2015
Eda Integration Engineer
Ibm Jul 2004 - Oct 2006
Asic Power Modeling and Estimation
Ibm Mar 1998 - Jul 2004
Asic Physical Design and Ip Enablement
Ibm Jun 1997 - Mar 1998
Manufacturing Quality Engineer
Education:
Purdue University 1987 - 1991
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Asic
Vlsi
Physical Design
Eda
Methodology
Cmos
Physical Verification
Integration
Semiconductors
Drc
Circuit Design
Cadence Virtuoso
Testing
Microprocessors
Modelsim
Ic
Perl
Debugging
Tcl
Very Large Scale Integration
Application Specific Integrated Circuits
Interests:
Education
Languages:
English

Publications

Us Patents

Method And System Of Modeling Leakage

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US Patent:
20070250797, Oct 25, 2007
Filed:
Apr 24, 2006
Appl. No.:
11/379844
Inventors:
James Engel - Cambridge VT, US
Susan Lichtensteiger - Essex Junction VT, US
Paul Sulva - Jericho VT, US
Larry Wissel - Williston VT, US
International Classification:
G06F 17/50
H03K 19/00
US Classification:
716002000, 716004000, 716017000
Abstract:
A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.
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Paul J Sulva from Jericho, VT, age ~55 Get Report