Search

Paul Stephen Gryskiewicz

from Chandler, AZ
Age ~56

Paul Gryskiewicz Phones & Addresses

  • 2831 Azalea Dr, Chandler, AZ 85224 (480) 917-5833
  • Payson, AZ
  • 1059 W Emerald Ave, Mesa, AZ 85210
  • 763 W Peralta Ave, Mesa, AZ 85210
  • Minneapolis, MN
  • Denver, CO
  • Maricopa, AZ
  • Phoenix, AZ

Work

Company: Intel corporation Sep 1994 Position: Engineering manager

Education

Degree: Master of Business Administration, Masters School / High School: Arizona State University - W. P. Carey School of Business 2002 to 2004

Skills

Soc • Semiconductors • Intel • Embedded Systems • Semiconductor Industry • Cross Functional Team Leadership • Debugging • Engineering Management • System Architecture • Ic • Device Drivers • Computer Architecture • Embedded Software • Team Leadership • Asic • Processors • Software Engineering • Consumer Electronics • Perl • Firmware • Set Top Box • Electrical Engineering • Electronics • Hardware Architecture • Arm • Microprocessors • Digital Tv • Pcie • Fpga • X86 • Simulations • Verilog • Hardware • Systemverilog • Wireless • Analog • Rtos • Software Development • Integrated Circuits • Application Specific Integrated Circuits • Strategic Planning • Mba • Digital Video • Digital Audio • Digital Signal Processing

Industries

Computer Hardware

Professional Records

Real Estate Brokers

Paul Gryskiewicz Photo 1

Paul Gryskiewicz, Chandler AZ Agent

View page
Work:
Prudential Arizona Properties
Chandler, AZ
(480) 385-1500 (Phone)

Resumes

Resumes

Paul Gryskiewicz Photo 2

Engineering Manager

View page
Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Computer Hardware
Work:
Intel Corporation
Engineering Manager
Education:
Arizona State University - W. P. Carey School of Business 2002 - 2004
Master of Business Administration, Masters
Arizona State University 1991 - 1993
Arizona State University 1988 - 1991
Bachelor of Science In Engineering, Bachelors, Electrical Engineering
Academy of Holy Angels
Arizona State University
Master of Business Administration, Masters, Business Administration
Skills:
Soc
Semiconductors
Intel
Embedded Systems
Semiconductor Industry
Cross Functional Team Leadership
Debugging
Engineering Management
System Architecture
Ic
Device Drivers
Computer Architecture
Embedded Software
Team Leadership
Asic
Processors
Software Engineering
Consumer Electronics
Perl
Firmware
Set Top Box
Electrical Engineering
Electronics
Hardware Architecture
Arm
Microprocessors
Digital Tv
Pcie
Fpga
X86
Simulations
Verilog
Hardware
Systemverilog
Wireless
Analog
Rtos
Software Development
Integrated Circuits
Application Specific Integrated Circuits
Strategic Planning
Mba
Digital Video
Digital Audio
Digital Signal Processing

Publications

Us Patents

Clock Selection For Processing Audio Data

View page
US Patent:
6421785, Jul 16, 2002
Filed:
Nov 3, 1998
Appl. No.:
09/185247
Inventors:
Paul S. Gryskiewicz - Chandler AZ
Karl H. Mauritz - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 108
US Classification:
713500
Abstract:
A circuit to provide one clock signal from a plurality of possible clock signals includes a register to receive indication of a data sampling frequency, a selection circuit operatively coupled to the register, the indicated data sampling frequency selecting one of a plurality of signals provided to the selection circuit, and a modification circuit to modify the selected signal based at least in part on the indicated sampling frequency. A method to automatically and dynamically provide one clock signal from a plurality of possible clock signals includes receiving a signal indicating a data sampling frequency, selecting one clock signal from a plurality of input clock signals based on the received data sampling frequency indication, and modifying the selected clock signal, based on the indicated sampling frequency, to generate an output clock signal. The modified selected signal (for the circuit) and the modified selected clock signal (for the method) may be provided as a clock signal to, for example, an audio processing circuit.

Blending Text And Graphics For Display On Televisions

View page
US Patent:
6545724, Apr 8, 2003
Filed:
Oct 29, 1999
Appl. No.:
09/430328
Inventors:
Paul S. Gryskiewicz - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 974
US Classification:
348597, 348598, 348578, 348587, 345641, 345589, 382162, 382165, 382261, 382266
Abstract:
Text and graphics elements may be alpha blended in a way to reduce flicker when the text or graphics are display by a processor-based television receiver. The alpha values are used to intelligently smooth pixels adjacent the element to create television text and graphics.

Synchronizing Video Streams With Different Pixel Clock Rates

View page
US Patent:
6573946, Jun 3, 2003
Filed:
Aug 31, 2000
Appl. No.:
09/652696
Inventors:
Paul S. Gryskiewicz - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 976
US Classification:
348600, 348589, 345629
Abstract:
Two independent visually displayable data streams may be synchronized in real-time. One data stream may be converted to look like the other data stream prior to mixing the two data streams together. One data stream is buffered while the other data stream is converted. A memory buffer is used to synchronize the two data streams.

Managing Alpha Values For Video Mixing Operations

View page
US Patent:
6646686, Nov 11, 2003
Filed:
Sep 21, 2000
Appl. No.:
09/666942
Inventors:
Paul S. Gryskiewicz - Chandler AZ
Aniruddha P. Joshi - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 974
US Classification:
348584, 348589, 348597
Abstract:
Alpha values associated with video mixing operations are sent to a memory on a low pin count bus. The memory is accessible to a video mixer, which retrieves the alpha values to perform a mixing operation. The alpha values for a field are sent to the memory during the field time for a previous field rather than during the vertical blanking interval. The alpha values may be compressed prior to transmission.

Programmably Controlling Video Formats

View page
US Patent:
6839093, Jan 4, 2005
Filed:
Nov 13, 1998
Appl. No.:
09/191764
Inventors:
Paul S. Gryskiewicz - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 546
H04N 5445
US Classification:
348555, 348554
Abstract:
A video controller may include at least one video input port which may be programmably configured to receive either RGB or non-RGB color space signals. The video controller may programmably operate in either an RGB or non-RGB mode. In this way, the number of color space conversions may be reduced in some embodiments. For example, where a television output device is coupled to the video controller, the video controller may provide a non-RGB output signal.

Adaptive Video Scaler

View page
US Patent:
6937291, Aug 30, 2005
Filed:
Aug 31, 2000
Appl. No.:
09/652694
Inventors:
Paul S. Gryskiewicz - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N009/74
US Classification:
348581, 348448, 348458, 348714, 348716, 345660, 345668, 358451, 382307
Abstract:
An adaptive filter is adjustable for performing scaling operations. During a scaling operation, the adaptive filter stores scaled data in a memory such that more data samples may be retrieved during a subsequent scaling operation. The size of a finite impulse response filter used during the subsequent scaling operation may be adjusted to access the additional data samples.

Blending Text And Graphics For Display

View page
US Patent:
RE39214, Aug 1, 2006
Filed:
Dec 19, 2003
Appl. No.:
10/742694
Inventors:
Paul S. Gryskiewicz - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 9/74
H04N 9/66
G09G 5/02
G09G 5/00
G09G 9/00
G09G 9/40
US Classification:
348597, 348598, 348578, 348587, 348641, 348589, 382162, 382165, 382261, 382266
Abstract:
Text and graphics elements may be alpha blended in a way to reduce flicker when the text or graphics are display by a processor-based television receiver. The alpha values are used to intelligently smooth pixels adjacent the element to create television text and graphics.

Programmably Controlling Video Formats

View page
US Patent:
7372505, May 13, 2008
Filed:
Dec 3, 2004
Appl. No.:
11/004603
Inventors:
Paul S. Gryskiewicz - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 5/56
H04N 5/445
US Classification:
348555, 348554, 345603
Abstract:
A video controller may include at least one video input port which may be programmably configured to receive either RGB or non-RGB color space signals. The video controller may programmably operate in either an RGB or non-RGB mode. In this way, the number of color space conversions may be reduced in some embodiments. For example, where a television output device is coupled to the video controller, the video controller may provide a non-RGB output signal.
Paul Stephen Gryskiewicz from Chandler, AZ, age ~56 Get Report