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Paul A Grudowski

from Austin, TX
Age ~53
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Also known as:
Paul Alexander Grudowski, Paula Grudowski, Paul I
Phone and address:
10501 Lockerbie Dr, Austin, TX 78750
(512) 257-1671
Related to:
Claude W Robertson, 76Amy G Chu, 55Hing Y Chu, 84Bryant G Chu, 41Linda H Chu, 70Millie S Chu, 73Raymond A Grudowski, 81Erica G Grudowski, 53Judith A Grudowski, 79
Connected to:
John S Grudza, 61Abbie A Grudzien, 45Arkadiusz Grudzien, 56Malgorzata Grudzien, 53Steven J Grudziecki, 55Caitlyn R Grudzinski, 33Dominik A Grudzinski, 36Jeremy S Grudzinski, 50Patrick J Grudzinsky, 51Benjamin Grue, 37

Paul Grudowski Phones & Addresses

  • 10501 Lockerbie Dr, Austin, TX 78750 (512) 257-1671
  • 4807 Marblehead Dr, Austin, TX 78727 (512) 834-9864
  • Port Aransas, TX

Work

Company: Nxp semiconductors Sep 1998 Position: Technical director

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The University of Texas at Austin 1989 to 1998 Specialities: Electrical Engineering

Skills

Process Integration • Cmos • Ic • Semiconductors • Silicon • Semiconductor Industry • Design of Experiments • Soc • Device Characterization • Yield • Analog • Failure Analysis • Jmp • Mixed Signal • Microelectronics • Processors • Cvd • Thin Films • Product Engineering • Transistors • Electrical Engineering • Characterization • Vlsi • Semiconductor Process • Microprocessors • Drc • Embedded Flash

Industries

Semiconductors

Resumes

Resumes

Paul Grudowski Photo 1

Technical Director

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Nxp Semiconductors
Technical Director
Education:
The University of Texas at Austin 1989 - 1998
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Process Integration
Cmos
Ic
Semiconductors
Silicon
Semiconductor Industry
Design of Experiments
Soc
Device Characterization
Yield
Analog
Failure Analysis
Jmp
Mixed Signal
Microelectronics
Processors
Cvd
Thin Films
Product Engineering
Transistors
Electrical Engineering
Characterization
Vlsi
Semiconductor Process
Microprocessors
Drc
Embedded Flash

Publications

Us Patents

Integrated Circuit Device And Method Therefor

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US Patent:
6846716, Jan 25, 2005
Filed:
Dec 16, 2003
Appl. No.:
10/737116
Inventors:
Geoffrey C-F Yeap - Austin TX, US
Srinivas Jallepalli - Austin TX, US
Yongjoo Jeon - Austin TX, US
James David Burnett - Austin TX, US
Rana P. Singh - Austin TX, US
Paul A. Grudowski - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21331
US Classification:
438367, 438366
Abstract:
A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Semiconductor Fabrication Process Using Transistor Spacers Of Differing Widths

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US Patent:
6864135, Mar 8, 2005
Filed:
Oct 31, 2002
Appl. No.:
10/285374
Inventors:
Paul A. Grudowski - Austin TX, US
Jian Chen - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/8238
US Classification:
438230, 438275
Abstract:
A semiconductor fabrication process is disclosed wherein a first gate () is formed over a first portion of a semiconductor substrate () and a second gate () is formed over a second portion of the substrate (). A spacer film () is deposited over substrate () and first and second gates (). First spacers () are then formed on sidewalls of the second gate () and second spacers () are formed on sidewalls of first gate (). The first and second spacers () have different widths. The process may further include forming first source/drain regions () in the substrate laterally disposed on either side of the first spacers () and second source/drain regions () are formed on either side of second spacers (). The different spacer widths may be achieved using masked first and second spacer etch processes () having different degrees of isotropy. The spacer etch mask and the source/drain implant mask may be common such that p-channel transistors have a different spacer width than n-channel transistors.

Transistor Sidewall Spacer Stress Modulation

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US Patent:
6902971, Jun 7, 2005
Filed:
Jul 21, 2003
Appl. No.:
10/624203
Inventors:
Paul A. Grudowski - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/8238
US Classification:
438218, 438353
Abstract:
A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode () over a gate dielectric () over a semiconductor substrate (). A spacer film () exhibiting a tensile stress characteristic is deposited over the gate electrode (). The stress characteristics of at least a portion of the spacer film is then modulated () and the spacer film () is etched to form sidewall spacers () on the gate electrode sidewalls. The spacer film () is an LPCVD silicon nitride in one embodiment. Modulating () the spacer film () includes implanting Xenon or Germanium into the spacers () at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant () may be performed selectively or non-selectively either before or after etching the spacer film ().

Transistor Sidewall Spacer Stress Modulation

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US Patent:
7132704, Nov 7, 2006
Filed:
Jan 13, 2005
Appl. No.:
11/036859
Inventors:
Paul A. Grudowski - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/76
US Classification:
257288, 257336, 257371, 257408, 257900, 257E21626, 257E2164
Abstract:
A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode () over a gate dielectric () over a semiconductor substrate (). A spacer film () exhibiting a tensile stress characteristic is deposited over the gate electrode (). The stress characteristics of at least a portion of the spacer film is then modulated () and the spacer film () is etched to form sidewall spacers () on the gate electrode sidewalls. The spacer film () is an LPCVD silicon nitride in one embodiment. Modulating () the spacer film () includes implanting Xenon or Germanium into the spacers () at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant () may be performed selectively or non-selectively either before or after etching the spacer film ().

Method Of Forming An Electronic Device

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US Patent:
7214590, May 8, 2007
Filed:
Apr 5, 2005
Appl. No.:
11/098874
Inventors:
Sangwoo Lim - Austin TX, US
Paul A. Grudowski - Austin TX, US
Mohamad M. Jahanbani - Austin TX, US
Hsing H. Tseng - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336
US Classification:
438287, 438585, 438591
Abstract:
A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.

Method Of Making A Nitrided Gate Dielectric

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US Patent:
7402472, Jul 22, 2008
Filed:
Feb 25, 2005
Appl. No.:
11/067257
Inventors:
Sangwoo Lim - Austin TX, US
Paul A. Grudowski - Austin TX, US
Tien Ying Luo - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
Hsing H. Tseng - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336
US Classification:
438197, 438287, 438591, 438769, 438775
Abstract:
A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

Anneal Of Epitaxial Layer In A Semiconductor Device

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US Patent:
7416605, Aug 26, 2008
Filed:
Jan 8, 2007
Appl. No.:
11/620987
Inventors:
Stefan Zollner - Austin TX, US
Veeraraghavan Dhandapani - Round Rock TX, US
Paul A. Grudowski - Austin TX, US
Gregory S. Spencer - Pflugerville TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
C30B 25/14
C30B 25/12
US Classification:
117 89, 117 4, 117 93, 117102
Abstract:
An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.

Electronic Device Including A Transistor Structure Having An Active Region Adjacent To A Stressor Layer And A Process For Forming The Electronic Device

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US Patent:
7420202, Sep 2, 2008
Filed:
Nov 8, 2005
Appl. No.:
11/269303
Inventors:
Vance H. Adams - Austin TX, US
Paul A. Grudowski - Austin TX, US
Venkat R. Kolagunta - Austin TX, US
Brian A. Winstead - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/06
H01L 21/31
US Classification:
257 18, 257 20, 257190, 257505, 257506, 257507, 257509, 257524, 438151, 438196, 438404, 438405, 438595, 438764, 438765, 438769, 438770, 438775, 438778, 438787, 438791, 372 45011
Abstract:
An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
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Paul A Grudowski from Austin, TX, age ~53 Get Report