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Paul G Filseth

from Los Gatos, CA
Age ~63

Paul Filseth Phones & Addresses

  • 230 Jensen Springs Rd, Los Gatos, CA 95033 (408) 353-9705
  • 15251 Old Ranch Rd, Los Gatos, CA 95033 (925) 461-1872
  • 2948 Amoroso Ct, Pleasanton, CA 94566 (925) 461-1872
  • Princeton, NJ
  • 3146 Bimber Ct, San Jose, CA 95148 (408) 223-2962
  • 12670 Brookpark Rd, Oakland, CA 94619
  • Newark, CA

Publications

Us Patents

Mask Correction Optimization

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US Patent:
6611953, Aug 26, 2003
Filed:
Jun 12, 2001
Appl. No.:
09/879846
Inventors:
Paul G. Filseth - Los Gatos CA
Mario Garza - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 19, 716 21
Abstract:
A mask is designed for use in a photolithographic process to offset effects of light diffraction. At least one region having a length along each edge of a mask feature is defined. Error values at selected points on the mask are derived from an aerial image of the mask features and a target light intensity measured during IC fabrication process development. A matrix is derived representing the contributions of light amplitude due to movement of each region in a direction normal to the region. The amount of movement of each region is based on least-squares fitting the linear expressions in the matrix to the error values. The amount of movement may be adjusted for movement of an adjacent region.

Optical And Etch Proximity Correction

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US Patent:
6701511, Mar 2, 2004
Filed:
Aug 13, 2001
Appl. No.:
09/928471
Inventors:
Paul G. Filseth - Los Gatos CA
Mario Garza - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 19
Abstract:
A method for adjusting preliminary feature position characteristics of a preliminary mask pattern on a mask to produce a desired etch pattern on a substrate having desired feature position characteristics.

Automatic Calibration Of A Masking Process Simulator

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US Patent:
6768958, Jul 27, 2004
Filed:
Nov 26, 2002
Appl. No.:
10/305673
Inventors:
Lav Ivanovic - Cupertino CA
Paul Filseth - Los Gatos CA
Mario Garza - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01P 2100
US Classification:
702 94
Abstract:
A method and system for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Wafer Process Critical Dimension, Alignment, And Registration Analysis Simulation Tool

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US Patent:
6782525, Aug 24, 2004
Filed:
Sep 5, 2002
Appl. No.:
10/236207
Inventors:
Mario Garza - Sunnyvale CA
Neal Callan - Lake Oswego OR
George Bailey - Welches OR
Travis Brist - Camas WA
Paul Filseth - Los Gatos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 19, 382144
Abstract:
An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Automatic Calibration Of A Masking Process Simulator

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US Patent:
6868355, Mar 15, 2005
Filed:
Apr 20, 2004
Appl. No.:
10/829408
Inventors:
Lav Ivanovic - Cupertino CA, US
Paul Filseth - Los Gatos CA, US
Mario Garza - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01P021/00
G06F019/00
US Classification:
702 94
Abstract:
A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Mask Correction For Photolithographic Processes

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US Patent:
6934410, Aug 23, 2005
Filed:
Jun 12, 2001
Appl. No.:
09/879664
Inventors:
Stanislav V. Aleshin - Moscow, RU
Marina M. Medvedeva - Moscow, RU
Eugeni E. Egorov - Moscow, RU
Gennady V. Belokopytov - Moscow, RU
Paul G. Filseth - Los Gatos CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06K009/00
US Classification:
382144, 382173, 382266, 382274, 355 53, 430 5, 716 19
Abstract:
Local images of photolithographic masks are assigned to classes based on similarity of functions of circuits formed by the images, so that all of the images of a class can be corrected by correcting one of the members. Boundaries of photolithographic masks are corrected for diffusion of light by moving regions based on process light intensity and proximity of close connections. Boundaries are also corrected for shifting of photoactive material in photoresists by calculating the amount of shift based on light intensities at pattern points.

Mask Defect Analysis For Both Horizontal And Vertical Processing Effects

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US Patent:
7149340, Dec 12, 2006
Filed:
Sep 20, 2002
Appl. No.:
10/251082
Inventors:
Paul Filseth - Los Gatos CA, US
Neal Callan - Lake Oswego OR, US
Kunal Taravade - Portland OR, US
Mario Garza - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06K 9/00
US Classification:
382144, 382141, 382149, 348126
Abstract:
A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Adaptive Sem Edge Recognition Algorithm

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US Patent:
7171047, Jan 30, 2007
Filed:
Dec 20, 2002
Appl. No.:
10/327452
Inventors:
Mikhail Grinchuk - San Jose CA, US
Lav Ivanovic - Cupertino CA, US
Paul Filseth - Los Gatos CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06K 9/48
US Classification:
382199
Abstract:
A computer-implemented method is disclosed for recognizing edges in a digital image having a plurality of pixels with gray-scale values defining features. The method includes recognizing edges of the features by cearting a new image in which pixels in the new image corresponding to pixels in the gray-scale image that have a brightness value meeting a predetermined threshold are assigned a first binary value to represent edge regions, while remaining pixels in the new image are assigned a second value to represent both background and internal areas of the features. Area recognition is then performed to distinguish internal feature areas from background areas. The method further includes detecting edge lines from the edge regions that separate features from background and internal feature areas.
Paul G Filseth from Los Gatos, CA, age ~63 Get Report