Patrick Alan Thompson

8531030, Sep 10, 2013

Dec 16, 2010

12/970464

Gregory Eric Howard - Plano TX, US
Patrick Thompson - Wylie TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/48

257737, 257E23032, 257E23035

An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.

20220384375, Dec 1, 2022

Aug 9, 2022

17/884284

- Dallas TX, US
Christopher Daniel Manack - Flower Mound TX, US
Nazila Dadvand - Sunnyvale CA, US
Salvatore Frank Pavone - Houston TX, US
Patrick Francis Thompson - Allen TX, US

H01L 23/00

In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

20230065075, Mar 2, 2023

Aug 31, 2021

17/463047

- Dallas TX, US
Vivek Swaminathan SRIDHARAN - Dallas TX, US
Christopher Daniel MANACK - Flower Mound TX, US
Patrick Francis THOMPSON - Allen TX, US
Jonathan Andrew MONTOYA - Dallas TX, US
Salvatore Frank PAVONE - Murphy TX, US

H01L 23/00

In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

20210210440, Jul 8, 2021

Jan 8, 2020

16/737237

- Dallas TX, US
Qiao Chen - Flower Mound TX, US
Michael Todd Wyant - Dallas TX, US
Matthew John Sherbin - Dallas TX, US
Patrick Francis Thompson - Allen TX, US

H01L 23/58
H01L 23/532
H01L 23/528

An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

20210210462, Jul 8, 2021

Jan 6, 2020

16/734836

- Dallas TX, US
Enis Tuncer - Dallas TX, US
Christopher Daniel Manack - Flower Mound TX, US
Patrick Francis Thompson - Allen TX, US

H01L 23/00

A semiconductor device includes a semiconductor surface having circuitry with metal interconnect layers over the semiconductor surface including a selected metal interconnect layer providing an interconnect trace having a first and second end. A top dielectric layer is on the top metal interconnect layer. A redistribution layer (RDL) is on the top dielectric layer. A corrosion interruption structure (CIS) including the interconnect trace bridges an interrupting gap in a trace of the RDL.