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Patrick R Pelletier

from Champaign, IL
Age ~47
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Also known as:
Rick R Pelletier, Patrick Pelltier, Patrick Pelliter
Phone and address:
1501 Kiler Dr APT 307, Champaign, IL 61820
Related to:
Leona A PelletierB EheartBettyjane J Eheart, 42Larry E Pelletier, 77Mariano Alonzo, 55Donald Eheart, 43Jane A Pelletier, 80Deanne K Bruns, 68Faith M Pelletier, 48Sean Korich, 48
Connected to:
Abigail G Pelletier, 30Annette Pelletier, 55Ariana Pelletier, 35Armand R Pelletier, 92Arnold G Pelletier, 70Barry L Pelletier, 68Bermont A Pelletier, 64Blake A Pelletier, 29Chloe M Pelletier, 34Christina Pelletier, 46

Patrick Pelletier Phones & Addresses

  • 1501 Kiler Dr APT 307, Champaign, IL 61820
  • Agoura Hills, CA
  • Rantoul, IL
  • Middleton, WI
  • Fitchburg, WI
  • Urbana, IL

Resumes

Resumes

Patrick Pelletier Photo 1

None

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Location:
Los Angeles, CA
Industry:
Computer Software
Work:

None
Oblong Industries Inc Jul 2008 - May 2014
G-Speak Engineer
Fulcrum Microsystems Sep 2001 - May 2008
Senior Software Engineer
Ghs Jun 1999 - Feb 2001
Systems Software Engineer
Symbios Logic Jun 1994 - Aug 1997
Summer Intern
Education:
University of Illinois at Urbana - Champaign 1997 - 1999
Bachelors, Bachelor of Science, Computer Science Massachusetts Institute of Technology 1993 - 1996
Skills:
C++
Perl
Device Drivers
Java
Ethernet
Embedded Software
Testing
Software Engineering
Distributed Systems
Software Development
C
Asic
Linux
Embedded Systems
Patrick Pelletier Photo 2

Patrick Pelletier

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Patrick Pelletier

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Patrick Pelletier Photo 4

Instructor At Los Angeles Mission College

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Location:
Greater Los Angeles Area
Industry:
Higher Education
Patrick Pelletier Photo 5

Patrick Pelletier

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Location:
United States
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Patrick Pelletier

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Location:
United States

Publications

Us Patents

Shared-Memory Switch Fabric Architecture

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US Patent:
20060155938, Jul 13, 2006
Filed:
Aug 18, 2005
Appl. No.:
11/208451
Inventors:
Uri Cummings - Santa Monica CA, US
Andrew Lines - Malibu CA, US
Patrick Pelletier - Agoura Hills CA, US
Robert Southworth - Chatsworth CA, US
Assignee:
Fulcrum Microsystems, Inc. - Calabasas CA
International Classification:
G06F 13/28
G06F 13/00
US Classification:
711149000, 710317000
Abstract:
A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory. The scheduling circuitry is further operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.

Shared-Memory Switch Fabric Architecture

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US Patent:
20100325370, Dec 23, 2010
Filed:
Aug 24, 2010
Appl. No.:
12/862539
Inventors:
Uri Cummings - Santa Monica CA, US
Andrew Lines - Malibu CA, US
Patrick Pelletier - Agoura Hills CA, US
Robert Southworth - Chatsworth CA, US
Assignee:
FULCRUM MICROSYSTEMS INC. - Calabasas CA
International Classification:
G06F 12/02
US Classification:
711149, 711E12013
Abstract:
A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory by sequentially querying the plurality of ports for the frames of data, and arbitrating among a subset of the ports having the frames of data to assign starting locations in the memory banks such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate.
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Patrick R Pelletier from Champaign, IL, age ~47 Get Report