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Patrick T Hickman

from Gilbert, AZ
Age ~70
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Also known as:
Patrick Te Hickman, Pat T Hickman, Partick T Hickman, William Hickman
Phone and address:
1728 Cortez Dr, Gilbert, AZ 85234
(480) 497-6767
Related to:
Cherie M Epple, 37
Connected to:
Abigail M Hickman, 48Angelia M Hickman, 51Asenath S Hickman, 41Barry L Hickman, 54Blake C Hickman, 40Brandan Hickman, 39Bridget G Hickman, 40Caryll M Hickman, 59Cecil R Hickman, 101Celia C Hickman, 65

Patrick Hickman Phones & Addresses

  • 1728 Cortez Dr, Gilbert, AZ 85234 (480) 497-6767 (480) 497-8900
  • 4430 Ficus Way, Gilbert, AZ 85298 (480) 497-8900 (480) 634-5475
  • 6386 Pinecone Ln, Pinetop, AZ 85935 (928) 369-4631
  • Tempe, AZ
  • Chandler, AZ
  • Nashville, TN
  • Maricopa, AZ
  • 4430 E Ficus Way, Gilbert, AZ 85298 (480) 206-6319

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

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Patrick Hickman

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Patrick Hickman

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Patrick Hickman

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Patrick Hickman

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Location:
United States
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Patrick Hickman

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Location:
United States
Industry:
Semiconductors
Patrick Hickman Photo 6

Analog Design Manager At Freescale Semiconductor

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Location:
United States
Industry:
Semiconductors
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Patrick Hickman

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Location:
United States
Patrick Hickman Photo 8

Patrick Hickman

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Patrick J Hickman
President
PATRICK J. HICKMAN, D.C., P.S

Publications

Us Patents

Programmable Block Architected Heterogeneous Integrated Circuit

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US Patent:
51553902, Oct 13, 1992
Filed:
Jul 25, 1991
Appl. No.:
7/735744
Inventors:
Patrick T. Hickman - Chandler AZ
Douglas W. Schucker - Mesa AZ
Jarvis Tou - Gilbert AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2710
H01L 2500
H03K 338
US Classification:
3074651
Abstract:
A block architected integrated circuit having predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures. The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit. As a result, these blocks must be adapted to readily fit within the power and signal grid structures of the integrated circuit.

Memory Efficient Gate Array Cell

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US Patent:
54522455, Sep 19, 1995
Filed:
Sep 7, 1993
Appl. No.:
8/124651
Inventors:
Patrick Hickman - Chandler AZ
Stephen W.-Y. Lai - Chandler AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 1140
US Classification:
365154
Abstract:
A core cell (10) for a gate array circuit has been provided. The core cell has a transistor layout that facilitates efficient memory circuit design within the gate array. The core cell includes a first (14-22) and second (23-31) plurality of transistors of a first conductivity type, and a third plurality (52-63) of transistors of a second conductivity type wherein the third plurality of transistors are positioned between the first and second plurality of transistors. The third plurality of transistors having transistors of a first and second size wherein at least two transistors of the second size of the third plurality of transistors includes a common gate connection.
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Patrick T Hickman from Gilbert, AZ, age ~70 Get Report