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Parviz G Ghazavi

from San Jose, CA
Age ~64
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Also known as:
Parviz P Ghazavi, Parviz G Ghazvi, Parviz Parviz, Parriz Ghazvi, Parviz H
Phone and address:
4745 San Lucas Way, San Jose, CA 95135
(408) 274-2002
Related to:
Khorasgani Hassan GhazaviHassan GhazaviNazafarine Nilchi, 54Nahid Ghazavi, 54
Connected to:
Mohammad Ghazavi, 38Mohammad T Ghazawi, 60Abdul H Ghazi, 27Amira S Ghazi, 51Betty K Ghazi, 72Bushra G Ghazi, 66Daniel A Ghazi, 52Ershi Ghazi, 37Fatemeh Ghazi, 74Hani N Ghazi, 40

Parviz Ghazavi Phones & Addresses

  • 4745 San Lucas Way, San Jose, CA 95135 (408) 274-2002
  • 4048 Rio Ct, San Jose, CA 95134
  • Huntsville, AL
  • Essie, KY
  • Sunnyvale, CA
  • 4745 San Lucas Way, San Jose, CA 95135

Publications

Us Patents

Array Of Split Gate Non-Volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates

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US Patent:
20130126958, May 23, 2013
Filed:
Nov 17, 2011
Appl. No.:
13/299320
Inventors:
Parviz Ghazavi - San Jose CA, US
Hieu Van Tran - San Jose CA, US
Nhan Do - Saratoga CA, US
International Classification:
H01L 27/088
US Classification:
257315, 257E2706
Abstract:
An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.

Method Of Determining Defective Die Containing Non-Volatile Memory Cells

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US Patent:
20230101585, Mar 30, 2023
Filed:
Jan 14, 2022
Appl. No.:
17/576754
Inventors:
- San Jose CA, US
JINHO KIM - Saratoga CA, US
CYNTHIA FUNG - San Jose CA, US
GILLES FESTES - Fuveau, FR
BERNARD BERTELLO - Greasque, FR
PARVIZ GHAZAVI - San Jose CA, US
BRUNO VILLARD - Aix en Provence, FR
JEAN FRANCOIS THIERY - Caromb, FR
CATHERINE DECOBERT - Pourrieres, FR
SERGUEI JOURBA - Ailx En Provence, FR
FAN LUO - Fremont CA, US
LATT TEE - San Francisco CA, US
NHAN DO - Saratoga CA, US
International Classification:
G11C 29/50
Abstract:
A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC for the memory cells and a first number N of the memory cells having the lowest read current RC. A second read operation is performed to determine a second number N of the memory cells having a read current not exceeding a target read current RC. The target read current RC is equal to the lowest read current RC plus a predetermined current value. The die is determined to be acceptable if the second number N is determined to exceed the first number N plus a predetermined number. The die is determined to be defective if the second number N is determined not to exceed the first number N plus the predetermined number.

Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide

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US Patent:
20210399127, Dec 23, 2021
Filed:
Jun 23, 2020
Appl. No.:
16/910022
Inventors:
- San Jose CA, US
Elizabeth Cuevas - Los Gatos CA, US
Yuri Tkachev - Sunnyvale CA, US
Parviz Ghazavi - San Jose CA, US
Bernard Bertello - Bouches du Rhones, FR
Gilles Festes - Fuveau, FR
Bruno Villard - Aix en Provence, FR
Catherine Decobert - Pourrieres, FR
Nhan Do - Saratoga CA, US
Jean Francois Thiery - Caromb, FR
International Classification:
H01L 29/788
H01L 29/66
H01L 27/11517
Abstract:
A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate

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US Patent:
20200395370, Dec 17, 2020
Filed:
Aug 27, 2020
Appl. No.:
17/005139
Inventors:
- San Jose CA, US
XIAN LIU - Sunnyvale CA, US
FENG ZHOU - Fremont CA, US
PARVIZ GHAZAVI - San Jose CA, US
STEVEN LEMKE - Boulder Creek CA, US
NHAN DO - Saratoga CA, US
Assignee:
Silicon Storage Technology,Inc. - San Jose CA
International Classification:
H01L 27/11536
H01L 27/11521
H01L 29/66
H01L 27/12
H01L 21/84
H01L 21/3205
H01L 21/3213
H01L 29/08
H01L 29/423
H01L 21/28
Abstract:
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate

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US Patent:
20190348427, Nov 14, 2019
Filed:
Aug 7, 2018
Appl. No.:
16/057749
Inventors:
- San Jose CA, US
Xian Liu - Sunnyvale CA, US
Feng Zhou - Fremont CA, US
Parviz Ghazavi - San Jose CA, US
Steve Lemke - Boulder Creek CA, US
Nhan Do - Saratoga CA, US
International Classification:
H01L 27/11536
H01L 27/12
H01L 21/84
H01L 21/3205
H01L 21/3213
H01L 29/08
H01L 29/66
H01L 27/11521
H01L 29/423
H01L 21/28
Abstract:
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Method Of Forming Memory Array And Logic Devices

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US Patent:
20170103991, Apr 13, 2017
Filed:
Sep 13, 2016
Appl. No.:
15/264457
Inventors:
- San Jose CA, US
CHIEN-SHENG SU - Saratoga CA, US
FENG ZHOU - Fremont CA, US
XIAN LIU - Sunnyvale CA, US
NHAN DO - Saratoga CA, US
PRATEEP TUNTASOOD - San Jose CA, US
PARVIZ GHAZAVI - San Jose CA, US
International Classification:
H01L 27/115
Abstract:
A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.
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Parviz G Ghazavi from San Jose, CA, age ~64 Get Report