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Panu Chaichanavong

from Sunnyvale, CA
Age ~46

Panu Chaichanavong Phones & Addresses

  • 1033 Scotia Ter UNIT 202, Sunnyvale, CA 94089
  • Mountain View, CA
  • San Diego, CA
  • Stanford, CA
  • Mc Farland, CA
  • New York, NY

Publications

Us Patents

Rate-28/30 Dc-Free Rll Code

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US Patent:
7436331, Oct 14, 2008
Filed:
Jan 24, 2007
Appl. No.:
11/657492
Inventors:
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03M 7/00
US Classification:
341 59, 341 58, 341 68, 341 69, 341 94
Abstract:
A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.

Method And Apparatus For Generating Non-Binary Balanced Codes

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US Patent:
7450040, Nov 11, 2008
Filed:
Jan 4, 2007
Appl. No.:
11/649899
Inventors:
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03M 7/00
US Classification:
341107
Abstract:
An encoder and method of decoding includes a grouping module that groups an input signal into a plurality of blocks, wherein the plurality of blocks include a current block and at least one prior block, wherein each of the plurality of blocks includes at least N symbols, and wherein each of the N symbols has one of q symbol values, where N is a positive integer and q is an integer greater than two. The encoder further includes a counting module that counts occurrences of the q symbol values in the at least one prior block to generate a first count and occurrences of the q symbol values in the current block to generate a second count. The encoder also includes a permutation module that selectively permutes the current block based on the first and second counts.

Rate-28/30 Dc-Free Rll Code

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US Patent:
7612697, Nov 3, 2009
Filed:
Oct 13, 2008
Appl. No.:
12/287763
Inventors:
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US
Assignee:
Marvell International Ltd - Hamilton
International Classification:
H03M 7/00
US Classification:
341 59, 341 58, 341 68, 341 69, 341 94
Abstract:
A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N−1 coding bits indicating whether corresponding ones of N−1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N−1 coding bits.

Method And Apparatus For Generating Non-Binary Balanced Codes

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US Patent:
7629903, Dec 8, 2009
Filed:
Feb 22, 2007
Appl. No.:
11/709385
Inventors:
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
H03M 7/00
US Classification:
341107, 341 50
Abstract:
A decoder comprises a grouping module that groups an input signal into a plurality of blocks and a plurality of permutation symbols, wherein the plurality of blocks include N symbols and wherein each of said N symbols has one of q symbol values, where q and N are integers greater than two. A permutation module inverse permutes a first block of the plurality of blocks based on one of the plurality of permutation symbols and generates a decoded output signal based on the permutation.

Enumerative Dc-Rll Constrained Coding

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US Patent:
7667626, Feb 23, 2010
Filed:
Apr 28, 2008
Appl. No.:
12/110921
Inventors:
Panu Chaichanavong - Mountain View CA, US
Gregory Burd - San Jose CA, US
Assignee:
Marvell International Ltd.
International Classification:
H03M 7/00
US Classification:
341 59, 341 58
Abstract:
Systems and methods are provided for encoding and decoding constrained codes using an enumerative coding graph. The constrained code may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has two branches that lead to other states. Each state in the enumerative coding graph is assigned a cardinality. Configuring the structure of the graph and the cardinalities associated with each state allow the encoder to generate a code that conforms to defined constraints.

Rate-7/8 Direct-Current Free And Runlength Limited Code

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US Patent:
7675436, Mar 9, 2010
Filed:
Sep 15, 2008
Appl. No.:
12/283648
Inventors:
Panu Chaichanavong - Mountain View CA, US
Zining Wu - Los Altos CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03M 5/00
US Classification:
341 58, 341 59
Abstract:
An encoder includes a mapping module that receives input words including first input words and second input words. The mapping module maps the first input words to first output words that are run-length limited and have a digital sum that is equal to zero. The mapping module maps the second input words to second output words that are run-length limited and have one of a positive and a negative digital sum. An inverter module selectively inverts the second output words based on a cumulative digital sum of the second output words.

Systems And Methods For Constructing High-Rate Constrained Codes

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US Patent:
7714748, May 11, 2010
Filed:
Jan 5, 2006
Appl. No.:
11/326727
Inventors:
Panu Chaichanavong - Mountain View CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03M 5/00
US Classification:
341 58, 341 59, 341 90, 341 94
Abstract:
A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Reduced-Complexity Decoding Of Parity Check Codes

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US Patent:
7752523, Jul 6, 2010
Filed:
Oct 16, 2006
Appl. No.:
11/582014
Inventors:
Panu Chaichanavong - Mountain View CA, US
Gregory Burd - San Jose CA, US
Assignee:
Marvell International Ltd.
International Classification:
H03M 13/00
US Classification:
714755, 714786, 714792, 714794, 714795, 714796, 714780, 375262, 375341
Abstract:
The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.
Panu Chaichanavong from Sunnyvale, CA, age ~46 Get Report