Pablo I Balzola

7593978, Sep 22, 2009

May 7, 2004

10/841261

Michael J. Schulte - Madison WI, US
Pablo I. Balzola - Nanuet NY, US
C. John Glossner - Carmel NY, US

Sandbridge Technologies, Inc. - White Plains NY

G06F 15/00

708603

A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

8539188, Sep 17, 2013

Jan 29, 2009

12/362329

Mayan Moudgill - White Plains NY, US
Vitaly Kalashnikov - Stamford CT, US
Murugappan Senthilvelan - Carmel NY, US
Umesh Srikantiah - Basking Ridge NJ, US
Tak-po Li - Nesconset NY, US
Pablo Balzola - Nanuet NY, US

QUALCOMM Incorporated - San Diego CA

G06F 12/14

711167, 711217, 711E12091

A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

20050060359, Mar 17, 2005

Jul 16, 2004

10/892686

Michael Schulte - Madison WI, US
Erdem Hokenek - Yorktown Heights NY, US
Pablo Balzola - Nanuet NY, US
C. Glossner - Carmel NY, US

G06F007/38

708495000

An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.