Search

Otto L Steinbusch

from San Diego, CA
Age ~50
Get Report
Also known as:
Otto L Lowery
Phone and address:
13713 Shoal Summit Dr, San Diego, CA 92128
(408) 386-7499
Related to:
Scott Joseph Hobin, 52Marita Jessica Wright, 50Taffy Steinbusch
Connected to:
Adam J Steinbuck, 53Anthony R Steinbuck, 64Jennifer L Steinburg, 52Kyle A Steinbuch, 45Michael J Steinbuchel, 81Keith L Steincamp, 59Brian W Steincke, 54Edgar K Steindal, 90Lisa K Steindel, 73Phillip A Steindel, 40

Otto Steinbusch Phones & Addresses

  • 13713 Shoal Summit Dr, San Diego, CA 92128 (408) 386-7499
  • Big Bear City, CA
  • 1011 Asbury Way, Mountain View, CA 94043 (408) 260-7947 (650) 966-8265
  • Palo Alto, CA
  • 10066 Pasadena Ave, Cupertino, CA 95014 (408) 253-2319
  • Santa Clara, CA
  • 13713 Shoal Summit Dr, San Diego, CA 92128

Work

Company: Pillsbury winthrop shaw pittman Nov 2010 Position: Patent agent and patent law clerk

Education

School / High School: University of San Diego School of Law 2012 to 2016

Skills

Patents • Intellectual Property • Asic • Semiconductors • Patent Prosecution • Patentability • Patent Applications • Embedded Systems • Ic • Client Counseling • Patent Litigation • Integrated Circuit Design • Programming • Microprocessors • Computer Graphics • Gpu • Dft • Automation • Unix • Patent Preparation • Patent Drafting • Patent Analysis • Patent Strategy • Patent Portfolio Management • Patent Development • Digital Design

Languages

English • Dutch

Ranks

Certificate: Registered Patent Agent

Industries

Law Practice

Resumes

Resumes

Otto Steinbusch Photo 1

Attorney

View page
Location:
13713 Shoal Summit Dr, San Diego, CA 92128
Industry:
Law Practice
Work:
Pillsbury Winthrop Shaw Pittman since Nov 2010
Patent Agent and Patent Law Clerk
Carr & Ferrell LLP May 2009 - Nov 2010
Patent Agent
NVIDIA 2004 - 2008
Sr. Asic Design engineer
Philips Semiconductors 2000 - 2004
Logic Designer
Philips Research 1998 - 2000
Research Scientist
Education:
University of San Diego School of Law 2012 - 2016
Technische Universiteit Eindhoven 1992 - 1998
Lorentz Lyceum (Gymnasium) 1986 - 1991
Skills:
Patents
Intellectual Property
Asic
Semiconductors
Patent Prosecution
Patentability
Patent Applications
Embedded Systems
Ic
Client Counseling
Patent Litigation
Integrated Circuit Design
Programming
Microprocessors
Computer Graphics
Gpu
Dft
Automation
Unix
Patent Preparation
Patent Drafting
Patent Analysis
Patent Strategy
Patent Portfolio Management
Patent Development
Digital Design
Languages:
English
Dutch
Certifications:
Registered Patent Agent
Uspto
Licensed California Attorney

Business Records

Name / Title
Company / Classification
Phones & Addresses
Otto Steinbusch
Senior Asic Design Engineer
NVIDIA
Computer Hardware · Mfg Semiconductors/Related Devices & Custom Computer Programming · Mfg Semiconductors/Related Devices and Custom Computer Programming · Radio and Television Broadcasting and Wireless Communication · Semiconductor and Related Device Manufacturing · Custom Computer Programming Svcs · Semiconductor Devices (Manufac
2701 San Tomas Expy, Santa Clara, CA 95050
561 E Elliot Rd #195, Chandler, AZ 85225
3535 Monroe St, Santa Clara, CA 95051
2860 San Tomas Expy, Santa Clara, CA 95051
(408) 486-2000, (408) 980-8001, (408) 486-2200, (408) 486-8236

Publications

Us Patents

Connecting Multiple Test Access Port Controllers On A Single Test Access Port

View page
US Patent:
7426670, Sep 16, 2008
Filed:
Dec 15, 2003
Appl. No.:
10/539104
Inventors:
Otto Steinbusch - Cupertino CA, US
Assignee:
NXP B.V. - Eindhoven
International Classification:
G06F 11/00
H04L 1/00
US Classification:
714747, 714727, 714 30, 714726
Abstract:
Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register () of each of a plurality of TAP controllers (), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

Automatic Resource Sharing Between Fifos

View page
US Patent:
7444491, Oct 28, 2008
Filed:
Dec 6, 2005
Appl. No.:
11/295940
Inventors:
Otto L. Steinbusch - Mountain View CA, US
Assignee:
nVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711170, 711171, 711172
Abstract:
Embodiments of the present invention recite a method and system for allocating memory resources. In one embodiment, a control component coupled with a memory device determines that a data buffer adjacent to a boundary of a first FIFO queue does not contain current data. The control component also determines that a second data buffer of a second FIFO queue adjacent to the boundary does not contain current data. The control component then automatically shifts the boundary to include the second data buffer in the first FIFO queue.

Lossless Transfer Of Events Across Clock Domains

View page
US Patent:
8284879, Oct 9, 2012
Filed:
Jun 25, 2004
Appl. No.:
10/562342
Inventors:
Otto Steinbusch - Mountain View CA, US
Marino Strik - Waalre, NL
Robert De Gruijl - San Francisco CA, US
Assignee:
NXP B.V. - Eindhoven
International Classification:
H04L 7/02
H04L 7/00
US Classification:
375354, 375359
Abstract:
Transfer circuits () for monitoring in a monitor clock domain target events that occur in a target clock domain () are disclosed. Some embodiments () impose significant constraints on the domain clocks and include: an event detector (); a sending circuit () that changes the value of a request signal () with each event; and a receiving circuit () that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter () that generates an incremental count () of event occurrences while a transfer is taking place; sending and receiving registers () for the incremental count; the request sending and receiving circuits (), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits () for an acknowledgement signal.

Method Of Executing A Computer Program With An Interpreter, Computer System And Computer Program Product

View page
US Patent:
20010052118, Dec 13, 2001
Filed:
Mar 19, 2001
Appl. No.:
09/811637
Inventors:
Otto Steinbusch - Cupertino CA, US
International Classification:
G06F009/45
US Classification:
717/008000
Abstract:
An interpreter uses a symbol table containing information for resolving symbolic references in instructions. Memory is provided for storing symbolic reference-result associations, the result of the association having resulted from resolving the symbolic reference of the association for an instruction. The memory is organized in groups of locations, each for results for a different category of instructions. During execution of a particular instruction, that group is consulted which is assigned to the category to which the particular instruction belongs. If that group contains an association for the symbolic reference in the particular instruction. If there is such an association, the result from the association is used as operand data for executing the particular instruction. If there is no such association, the particular symbolic reference is resolved by means of the symbol table. The result from said resolving is used as the operand data for executing the particular instruction and an association between the symbolic reference and the result of said resolving is stored in the group assigned to the category of the particular instruction.

Low Overhead Exception Checking

View page
US Patent:
20030093456, May 15, 2003
Filed:
Oct 22, 2002
Appl. No.:
10/277538
Inventors:
Otto Steinbusch - Cupertino CA, US
Menno Lindwer - Eindhoven, NL
International Classification:
G06F017/00
US Classification:
709/001000
Abstract:
Exception detection is expedited in virtual machine interpreter (VMI) accelerator hardware () by dispatching fetched bytecodes along with instructions that cause a processor interrupt if the fetched bytecodes cause an exception to be thrown. The processor interrupt serves to indicate to the VMI () that an exception condition exists, thereby obviating the need to for the VMI () to wait for the result of an exception check to be sent from the CPU () to the VMI ().

Power Management Using Automatic Load/Unload Detection Of Dac

View page
US Patent:
20090158066, Jun 18, 2009
Filed:
Dec 14, 2007
Appl. No.:
12/002166
Inventors:
Otto Steinbusch - Mountain View CA, US
Zahid Najam - San Jose CA, US
International Classification:
G06F 1/32
G06F 1/00
US Classification:
713322, 713300
Abstract:
An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power.
Control profile
Otto L Steinbusch from San Diego, CA, age ~50 Get Report