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Otomar Schmidt

from Richmond Heights, OH
Age ~74
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Also known as:
Schmidt Otomar
Phone and address:
25416 Pleasant Trl, Cleveland, OH 44143
(216) 481-2578
Related to:
Antonio Scanziello, 66Kate L Vargo, 56Adam C Krafcheck, 40Shirley M Kosisko, 89Paula J Fatica, 58Pamela A Schmidt, 68Kristen E Schmidt, 33James J Kosisko, 66
Connected to:
Abby K Schmidt, 41Addison T Schmidt, 29Adrien Schmidt, 47Aiko Y Schmidt, 83Aileen M Schmidt, 75Alden T Schmidt, 83Alena R Schmidt, 99Alexandria Schmidt, 31Alyssa R Schmidt, 37Amanda Schmidt, 37

Otomar Schmidt Phones & Addresses

  • 25416 Pleasant Trl, Richmond Heights, OH 44143 (216) 481-2578
  • 25416 Pleasant St, Richmond Heights, OH 44143
  • Cleveland, OH
  • North Olmsted, OH
  • Willoughby Hills, OH

Work

Position: Senior project engineer

Resumes

Resumes

Otomar Schmidt Photo 1

Senior Project Engineer

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Location:
Cleveland, OH
Work:

Senior Project Engineer

Publications

Us Patents

Bi-Directional Co-Processor Interface

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US Patent:
57154392, Feb 3, 1998
Filed:
Dec 9, 1996
Appl. No.:
8/762650
Inventors:
Otomar Schmidt - Richmond Heights OH
Richard S. Gunsaulus - Highland Heights OH
Ronald E. Schultz - Solon OH
Charles M. Rischar - Chardon OH
Jeffrey W. Brooks - Mentor-On-The-Lake OH
Assignee:
Allen-Bradley Company, Inc. - Milwaukee WI
International Classification:
G06F 9455
US Classification:
395570
Abstract:
A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.

Program Analysis Circuitry For Multi-Tasking Industrial Controller

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US Patent:
56194099, Apr 8, 1997
Filed:
Jun 12, 1995
Appl. No.:
8/489422
Inventors:
Ronald E. Schultz - Solon OH
Charles M. Rischar - Chardon OH
Richard S. Gunsaulus - Highland Heights OH
Otomar Schmidt - Richmond Heights OH
Assignee:
Allen-Bradley Company, Inc. - Milwaukee WI
International Classification:
G06F 1900
G06F 946
US Classification:
364146
Abstract:
A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common "global" memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.

Integrated Relay Ladder Language, Reduced Instruction Set Computer

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US Patent:
60187972, Jan 25, 2000
Filed:
Dec 9, 1997
Appl. No.:
8/987033
Inventors:
Otomar Schmidt - Richmond Heights OH
Richard S. Gunsaulus - Highland Heights OH
Ronald E. Schultz - Solon OH
Jeffery W. Brooks - Mentor-On-The-Lake OH
Assignee:
Allen-Bradley Company, LLC - Milwaukee WI
International Classification:
G06F 1578
US Classification:
712 42
Abstract:
An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.

Industrial Controller Permitting Program Editing During Program Execution

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US Patent:
57817766, Jul 14, 1998
Filed:
Nov 1, 1995
Appl. No.:
8/551441
Inventors:
David A. Johnston - Mentor OH
Charles M. Rischar - Chardon OH
Ronald E. Schultz - Solon OH
Otomar Schmidt - Richmond Heights OH
Assignee:
Allen Bradley Company, Inc. - Milwaukee WI
International Classification:
G06F 944
US Classification:
395704
Abstract:
A method of editing a real-time control program as it controls equipment is provided in which the editing occurs in a second area of memory and integrated into the pre-existing program by means of conditional jump instructions concatenated to that edited material. The pre-existing program is uninterrupted by the editing process except for a change of single instructions which do not affect the results of the execution but redirect the execution thread of that control program to be conditionally connected to the edited material. This single writing of single instructions, which do not affect execution results, precludes the possibility of the controller executing partially edited programs. The jump instructions are conditional on a test edit pointer to allow instantaneous implementation of the edits and a simple return to unedited instructions simply by changing the state of the flag.

Processor For A Programmable Controller

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US Patent:
52650057, Nov 23, 1993
Filed:
Dec 29, 1992
Appl. No.:
7/998178
Inventors:
Otomar S. Schmidt - Richmond Heights OH
Raymond R. Husted - Mentor OH
Wayne Van Sickle - South Euclid OH
Terrence L. Dauterman - Chardon OH
David R. Rohn - Richmond Heights OH
Assignee:
Allen-Bradley Company, Inc. - Milwaukee WI
International Classification:
G05B 1900
US Classification:
364147
Abstract:
A programmable controller has a rack that electrically connects a number of I/O modules to a processor module. The processor module includes a external device communication interface section and a general purpose processor section electrically coupled together by a set of common buses. Both of these module sections include a microprocessor and memory connected by an internal set of buses which are isolatable from the set of common buses. The isolation capability permits the different sections to perform their operations simultaneously. A shared system memory and an rack interface are coupled to the common buses for the exchange of data with the I/O modules. A unique ladder logic processor also is connected directly to the common buses. The ladder logic processor includes a hardwired Boolean bit logic processor and a custom microcoded processor to execute instructions of a ladder type control program. Program instructions which are too complex for execution by the ladder logic processor are executed by the general purpose processor section.

Programmable Controller Processor Module Having Multiple Program Instruction Execution Sections

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US Patent:
52126315, May 18, 1993
Filed:
Apr 24, 1992
Appl. No.:
7/874994
Inventors:
Otomar S. Schmidt - Richmond Heights OH
Raymond R. Husted - Mentor OH
Wayne Van Sickle - South Euclid OH
Terrence L. Dauterman - Chardon OH
David R. Rohn - Richmond Heights OH
Assignee:
Allen-Bradley Company, Inc. - Milwaukee WI
International Classification:
G05B 1905
US Classification:
364136
Abstract:
A programmable controller has a rack that electrically connects a number of I/O modules to a processor module. The processor module includes a external device communication interface section and a general purpose processor section electrically coupled together by a set of common buses. Both of these module sections include a microprocessor and memory connected by an internal set of buses which are isolatable from the set of common buses. The isolation capability permits the different sections to perform their operations simultaneously. A shared system memory and an rack interface are coupled to the common buses for the exchange of data with the I/O modules. A unique ladder logic processor also is connected directly to the common buses. The ladder logic processor includes a hardwired Boolean bit logic processor and a custom microcoded processor to execute instructions of a ladder type control program. Program instructions which are too complex for execution by the ladder logic processor are executed by the general purpose processor section.

Industrial Controller Permitting Removal And Insertion Of Circuit Cards While Under Power

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US Patent:
59832983, Nov 9, 1999
Filed:
Nov 20, 1995
Appl. No.:
8/561506
Inventors:
Ronald E. Schultz - Solon OH
William E. Floro - Willoughby OH
Otomar Schmidt - Richmond Heights OH
Assignee:
Allen-Bradley Company, LLC - Milwaukee WI
International Classification:
G06F 1300
US Classification:
710103
Abstract:
A circuit card of an industrial controller may be removed or inserted under power without loss of memory or disturbance to the power supplies of other modules through the use of a power failure signal derived from shortened pins on the connector between the card and the industrial controller. The power failure signal activates a timer delaying connection of the board components to power until the physical connection between the card and the industrial controller has stabilized. At this time current drain is ramped up by a controlling series FET. Upon removal of the card, the power failure signal causes outputs of an on-board microprocessor to be pulled to particular states necessary to prevent disturbance of a battery backed-up RAM and to eliminate current flow through protection diodes on other memory type devices attached to the microprocessor.

Computer Memory System Providing Parity With Standard Non-Parity Memory Devices

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US Patent:
59149701, Jun 22, 1999
Filed:
Aug 27, 1997
Appl. No.:
8/921730
Inventors:
Richard S. Gunsaulus - Highland Heights OH
Otomar S. Schmidt - Richmond Heights OH
Assignee:
Allen-Bradley Company, LLC - Milwaukee WI
International Classification:
G06F 1110
H03M 1300
US Classification:
371 511
Abstract:
A memory system uses standard memory devices not normally supporting parity bits. Parity bits for multiple memory devices are stored in a dedicated parity device shared among multiple memory devices. Inadvertent erasure of the parity information, when writing to a single memory device, is prevented by a prereading of the parity device prior to a writing to the single memory device. Special circuitry stores the preread parity information and merges it back with the calculated parity bit for the written data to preserve complete parity information.
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Otomar Schmidt from Richmond Heights, OH, age ~74 Get Report