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Oliver David Skull

from Lafayette, CO
Age ~51
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Also known as:
Oliver D Skull, David Skull Oliver, Skull L Oliver
Phone and address:
1293 Ceres Dr, Lafayette, CO 80026
(303) 666-8942
Related to:
Louis L Skull, 56Pete Skull, 56A Skull, 77
Connected to:
Stephen L Skullerud, 82Bryan M Skulley, 51Daniel G Skully, 58Michael E Skully, 52Stacie L Skully, 56Amy S Skulnik, 52David Skulnik, 82Richard M Skulnik, 43Robert J Skulnik, 60Alicia L Skulski, 60

Oliver Skull Phones & Addresses

  • 1293 Ceres Dr, Lafayette, CO 80026 (303) 666-8942
  • Twin Lakes, CO
  • Denver, CO

Work

Company: Ball aerospace Dec 2018 Position: Principle fpga design engineer

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: University of Colorado Denver 1992 to 1997 Specialities: Electrical Engineering

Skills

Fpga • Asic • Digital Signal Processors • Verilog • Debugging • Vlsi • Embedded Systems • Digital Signal Processing • Field Programmable Gate Arrays • Matlab • Simulink • Mpeg2 • H.264 • Ntsc • Pal • Dsp • Rtos • Api • C • Algorithm Design • Digital Video • Signal Processing • Simulation • System on A Chip • Python • Embedded Software • Firmware • C (Programming Language • Video Processing • Filters • Filter Design • Rtl Coding • Logic Design • Universal Verification Methodology • Systemverilog • Silicon Debug

Industries

Computer Hardware

Resumes

Resumes

Oliver Skull Photo 1

Principle Fpga Design Engineer

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Location:
1293 Ceres Dr, Lafayette, CO 80026
Industry:
Computer Hardware
Work:
Ball Aerospace
Principle Fpga Design Engineer
Seagate Technology Oct 2015 - Dec 2018
Senior Staff Design Engineer
Dot Hill Systems Feb 2012 - Oct 2015
Senior Asic Design Engineer
Microtune Sep 2006 - Aug 2011
Staff Architecture and Algorithms Engineer
Digeo May 2002 - Jul 2006
Senior Vlsi Design Engineer
Education:
University of Colorado Denver 1992 - 1997
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Fpga
Asic
Digital Signal Processors
Verilog
Debugging
Vlsi
Embedded Systems
Digital Signal Processing
Field Programmable Gate Arrays
Matlab
Simulink
Mpeg2
H.264
Ntsc
Pal
Dsp
Rtos
Api
C
Algorithm Design
Digital Video
Signal Processing
Simulation
System on A Chip
Python
Embedded Software
Firmware
C (Programming Language
Video Processing
Filters
Filter Design
Rtl Coding
Logic Design
Universal Verification Methodology
Systemverilog
Silicon Debug

Publications

Us Patents

Systems And Methods Providing In-Phase And Quadrature Equalization

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US Patent:
8306103, Nov 6, 2012
Filed:
Dec 7, 2009
Appl. No.:
12/632624
Inventors:
Oliver Skull - Lafayette CO, US
Stephane Laurent-Michel - Longmont CO, US
Alan Doak - Boulder CO, US
Assignee:
CSR Technology Inc. - Sunnyvale CA
International Classification:
H03H 7/30
H04B 1/10
US Classification:
375232, 375350
Abstract:
Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Multimode Filter Architecture

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US Patent:
8416899, Apr 9, 2013
Filed:
Dec 7, 2009
Appl. No.:
12/632634
Inventors:
Stephane Laurent-Michel - Longmont CO, US
Oliver Skull - Lafayette CO, US
Alan Doak - Boulder CO, US
Assignee:
CSR Technology Inc. - Sunnyvale CA
International Classification:
H04B 1/10
US Classification:
375350
Abstract:
Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
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Oliver David Skull from Lafayette, CO, age ~51 Get Report