Nobuo Kojima from Cupertino, CA, age 56

Resumes

Nobuo Kojima

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Publications

Us Patents

Set-Associative Cache Memory Having A Built-In Set Prediction Array

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US Patent:

6356990, Mar 12, 2002

Filed:

Feb 2, 2000

Appl. No.:

09/496474

Inventors:

Naoaki Aoki - Austin TX
Sang Hoo Dhong - Austin TX
Nobuo Kojima - Austin TX
Joel Abraham Silberman - Somers NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711205, 711128

Abstract:

A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.

Edge-Triggered Latch With Symmetric Complementary Pass-Transistor Logic Data Path

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US Patent:

6437624, Aug 20, 2002

Filed:

Mar 15, 2001

Appl. No.:

09/810027

Inventors:

Nobuo Kojima - Austin TX
Huajun Wen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3356

US Classification:

327211, 327218

Abstract:

An edge-triggered latch having improved clock-to-output performance and greater efficiency. The edge-triggered latch of the present invention includes a data input and a clock input. Multiple source-to-drain connected pass-transistor logic (PTL) transistors are incorporated in the data path of the edge-triggered latch for converting a clock signal from the clock input into an edge-triggered data evaluation window. The PTL transistors propagate data from the data input into a storage node during the edge-triggered data evaluation window.

Edge-Triggered Latch With Balanced Pass-Transistor Logic Trigger

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US Patent:

6445217, Sep 3, 2002

Filed:

Mar 15, 2001

Appl. No.:

09/810026

Inventors:

Nobuo Kojima - Austin TX
Kevin John Nowka - Round Rock TX
Huajun Wen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 345

US Classification:

327 57, 327 51, 327 52

Abstract:

An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Processor Cycle Time Independent Pipeline Cache And Method For Pipelining Data From A Cache

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US Patent:

6453390, Sep 17, 2002

Filed:

Dec 10, 1999

Appl. No.:

09/458405

Inventors:

Naoaki Aoki - Austin TX
Sang Hoo Dhong - Austin TX
Nobuo Kojima - Austin TX
Joel Abraham Silberman - Somers NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711140, 711169

Abstract:

A processor cycle time independent pipeline cache and method for pipelining data from a cache provide a processor with operand data and instructions without introducing additional latency for synchronization when processor frequency is lowered or when a reload port provides a value a cycle earlier than a read access from the cache storage. The cache incorporates a persistent data bus that synchronizes the stored data access with the pipeline and can also utilize bypass mode data available from a cache input from the lower level when data is being written to the cache.

5-To-2 Binary Adder

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US Patent:

6578063, Jun 10, 2003

Filed:

Jun 1, 2000

Appl. No.:

09/584893

Inventors:

Nobuo Kojima - Austin TX
Ohsang Kwon - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

708708, 708709

Abstract:

A five-input/two-output binary adder is disclosed. The five-input/two-output adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the five inputs and generating a sum value and a carry value at the outputs.

4 To 2 Adder

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US Patent:

6584485, Jun 24, 2003

Filed:

Apr 14, 2000

Appl. No.:

09/549766

Inventors:

Naoaki Aoki - Austin TX
Sang Hoo Dhong - Austin TX
Nobuo Kojima - Austin TX
Ohsang Kwon - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

708708, 708709, 708710

Abstract:

A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR block and a MUX block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Method And Apparatus For Generating True/Complement Signals

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US Patent:

6239620, May 29, 2001

Filed:

Nov 29, 1999

Appl. No.:

9/450982

Inventors:

Naoaki Aoki - Austin TX
Sang Hoo Dhong - Austin TX
Nobuo Kojima - Austin TX
Joel Abraham Silberman - Somers NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 33568

US Classification:

326 95

Abstract:

A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.