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Noah L Sherrill

from Long Beach, CA
Age ~42
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Also known as:
Noah Lewis Sherrill
Related to:
Samuel B Sherrill, 32Donna SherrillLewis C Sherrill, 95Hannah I Sherrill, 35Robert L Sherrill, 67Rachel C Sherrill, 40Christopher J Lupo, 48Kasey W Sherrill, 65
Connected to:
Alexander J Sherrington, 41Alice W Sherrill, 72Alicia A Sherrill, 54Alquinn Sherrill, 33Anietra L Sherrill, 57April M Sherrill, 44Betty P Sherrill, 96Bob H Sherrill, 72Bonnie J Sherrill, 68Bryant J Sherrill, 36

Noah Sherrill Phones & Addresses

  • Long Beach, CA
  • Austin, TX
  • Avalon, CA
  • Laramie, WY
  • Bellevue, WA
  • Woodinville, WA
  • Fort Bragg, NC
  • Chino Hills, CA
  • 411 W Seaside Way UNIT 801, Long Beach, CA 90802

Resumes

Resumes

Noah Sherrill Photo 1

Senior Engineer

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Location:
8200 Farmington Ct, Austin, TX 78736
Industry:
Computer Software
Work:
Huawei Technologies
Senior Engineer
Liferay, Inc Apr 2017 - Mar 2018
Software Engineer
Msc Software Apr 2014 - Mar 2017
Development Engineer 1
Education:
California State University, Long Beach 2011 - 2014
Master of Science, Masters, Computer Science University of Washington 2001 - 2006
Bachelors, Bachelor of Science, Applied Mathematics
Skills:
Programming
Bookkeeping
C++
Python
Software Development
Java
Interests:
Politics
Science and Technology
Languages:
English
Noah Sherrill Photo 2

Forklift Operator

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Work:
Efp
Forklift Operator

Publications

Us Patents

Pseudorandom Thread Generation

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US Patent:
20230097765, Mar 30, 2023
Filed:
Dec 2, 2022
Appl. No.:
18/061224
Inventors:
- Shenzhen, CN
Noah Lewis Sherrill - Austin TX, US
International Classification:
G06F 9/48
G06F 7/58
Abstract:
Implementations are directed to methods, systems, and computer-readable media for scheduling threads for instruction sequence generation. In one aspect, scheduling threads for instruction sequence generation can include obtaining a model of a central processing unit (CPU) that includes a plurality of threads, wherein the model includes a plurality of model threads that correspond to the plurality of threads of the CPU. A seed value can be input into a pseudorandom number generator and in response to the input seed value, a sequence of pseudorandom values can be obtained from the pseudorandom number generator. Using the sequence of pseudorandom values and a thread scheduling algorithm, a thread execution order of the plurality of model can be generated.

Resumable Instruction Generation

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US Patent:
20230101154, Mar 30, 2023
Filed:
Dec 2, 2022
Appl. No.:
18/074167
Inventors:
- Shenzhen, CN
Michael Vaden - Austin TX, US
Jingliang Wang - Austin TX, US
Noah Sherrill - Austin TX, US
Stephen Edwards - Austin TX, US
International Classification:
G06F 11/36
Abstract:
A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.

Configurable State Transition

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US Patent:
20230091478, Mar 23, 2023
Filed:
Nov 28, 2022
Appl. No.:
18/070270
Inventors:
- shenzhen, CN
Noah Sherrill - Austin TX, US
Assignee:
HUAWEI TECHNOLOGIES CO., LTD. - Shenzhen
International Classification:
G06F 30/3308
G06F 30/337
Abstract:
According to one aspect of the present disclosure a system and method of enhancing random test case generation during pre-silicon design verification of test models of very large scale integration (VLSI) processors and systems is provided. A test sequence including a specification of at least one target state value for at least one resource of the hardware design model is received and includes a state object having at least one state element defining the target state value for a resource. Instructions are generated to transition the at least one resource from an existing state to the at least one target state value. The instructions are executed according to the test sequence to transition the resources to the defined state. State information on the hardware design model is output to allow a process engineer to determine whether the target state value for the resource was successfully changed.
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Noah L Sherrill from Long Beach, CA, age ~42 Get Report