Resumes
Resumes
Customer Engagement Architect
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Cadence Design Systems
Customer Engagement Architect
Cadence Design Systems Jun 1, 2016 - Jul 2019
Senior Principal Product Engineer
Cadence Design Systems Sep 2015 - Jun 2016
Principal Product Engineer
Intel Corporation Apr 2015 - Sep 2015
Senior Verification Engineer
Cadence Design Systems Jul 2013 - Apr 2015
Principal Application Engineer
Customer Engagement Architect
Cadence Design Systems Jun 1, 2016 - Jul 2019
Senior Principal Product Engineer
Cadence Design Systems Sep 2015 - Jun 2016
Principal Product Engineer
Intel Corporation Apr 2015 - Sep 2015
Senior Verification Engineer
Cadence Design Systems Jul 2013 - Apr 2015
Principal Application Engineer
Education:
Ben - Gurion University of the Negev 2000 - 2004
Bachelors, Bachelor of Science, Engineering
Bachelors, Bachelor of Science, Engineering
Skills:
Functional Verification
Soc
Specman
Systemverilog
Verilog
Eda
Debugging
Ncsim
Simulations
Uvm
Vhdl
Cadence
Rtl Coding
Universal Verification Methodology
Field Programmable Gate Arrays
Soc
Specman
Systemverilog
Verilog
Eda
Debugging
Ncsim
Simulations
Uvm
Vhdl
Cadence
Rtl Coding
Universal Verification Methodology
Field Programmable Gate Arrays
Languages:
Hebrew
English
English