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Ningde Xie

from Portland, OR
Age ~40
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Connected to:
Aihua H Xie, 60Alice Xie, 27Angela Xie, 61Anita Xie, 34April M Xie, 61Betty L Xie, 56Bike Xie, 37Calvin Xie, 43Cathy Z Xie, 31Chengyu Xie, 41

Ningde Xie Phones & Addresses

  • Portland, OR
  • Hillsboro, OR
  • Troy, NY
  • 2747 NE 9Th Dr, Hillsboro, OR 97124

Work

Company: Intel corporation Apr 2010 to Aug 2013 Position: Sr. hardware engineer

Education

Degree: PhD School / High School: Rensselaer Polytechnic Institute 2006 to 2010 Specialities: Electrical Engineering

Industries

Semiconductors

Resumes

Resumes

Ningde Xie Photo 1

Storage And Communications Professional

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Position:
Sr. Hardware Engineer at Intel Corporation
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Intel Corporation since Apr 2010
Sr. Hardware Engineer
NEC Laboratories America Apr 2009 - Aug 2009
Internship
Education:
Rensselaer Polytechnic Institute 2006 - 2010
PhD, Electrical Engineering Southeast University 2004 - 2006
MS, electrical engineering Southeast University 2000 - 2004
BS, electrical engineering

Publications

Us Patents

Adjustable Programming Speed For Nand Memory Devices

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US Patent:
2012022, Sep 6, 2012
Filed:
Mar 3, 2011
Appl. No.:
13/039553
Inventors:
Ningde Xie - Hillsboro OR,
Matthew Goldman - Folsom CA,
Jawad B. Khan - Cornelius OR,
Robert W. Faber - Hillsboro OR,
International Classification:
H03M 13/05
G06F 11/10
US Classification:
714763, 714E11034
Abstract:
Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Method And System For Data De-Duplication

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US Patent:
2013031, Nov 28, 2013
Filed:
Dec 20, 2011
Appl. No.:
13/977069
Inventors:
Jawad B. Khan - Cornelius OR,
Ningde Xie - Hillsboro OR,
Raj K. Ramanujan - Federal Way WA,
Leena K. Puthiyedath - Beaverton OR,
International Classification:
G06F 12/02
US Classification:
711103
Abstract:
An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
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Ningde Xie from Portland, OR, age ~40 Get Report