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Ningde Xie

from Portland, OR
Age ~43
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Connected to:
Aihua H Xie, 64Alice Xie, 31Angela Xie, 65Anita Xie, 38April M Xie, 65Betty L Xie, 60Bike Xie, 41Calvin Xie, 47Cathy Z Xie, 35Chengyu Xie, 45

Ningde Xie Phones & Addresses

  • 5225 SW Laurelwood Ave, Portland, OR 97225
  • Beaverton, OR
  • Troy, NY
  • 2747 NE 9Th Dr, Hillsboro, OR 97124

Work

Company: Intel corporation Apr 2010 Position: Sr. hardware engineer

Education

Degree: PhD School / High School: Rensselaer Polytechnic Institute 2006 to 2010 Specialities: Electrical Engineering

Skills

Storage • Hadoop • Fpga • Ic • Computer Architecture • Big Data • Firmware • Perl • Vhdl • Hardware Architecture • Rtl Design • Device Drivers • Tcl • Embedded Software • Eda • Analog • Analog Circuit Design • Cmos • Matlab • Circuit Design

Languages

Mandarin • English

Industries

Semiconductors

Resumes

Resumes

Ningde Xie Photo 1

Cofounder, Chief Technology Officer

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Intel Corporation since Apr 2010
Sr. Hardware Engineer
NEC Laboratories America Apr 2009 - Aug 2009
Internship
Education:
Rensselaer Polytechnic Institute 2006 - 2010
PhD, Electrical Engineering Southeast University 2004 - 2006
MS, electrical engineering Southeast University 2000 - 2004
BS, electrical engineering
Skills:
Storage
Hadoop
Fpga
Ic
Computer Architecture
Big Data
Firmware
Perl
Vhdl
Hardware Architecture
Rtl Design
Device Drivers
Tcl
Embedded Software
Eda
Analog
Analog Circuit Design
Cmos
Matlab
Circuit Design
Languages:
Mandarin
English

Publications

Us Patents

Adjustable Programming Speed For Nand Memory Devices

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US Patent:
20120226959, Sep 6, 2012
Filed:
Mar 3, 2011
Appl. No.:
13/039553
Inventors:
Ningde Xie - Hillsboro OR, US
Matthew Goldman - Folsom CA, US
Jawad B. Khan - Cornelius OR, US
Robert W. Faber - Hillsboro OR, US
International Classification:
H03M 13/05
G06F 11/10
US Classification:
714763, 714E11034
Abstract:
Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Method And System For Data De-Duplication

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US Patent:
20130318288, Nov 28, 2013
Filed:
Dec 20, 2011
Appl. No.:
13/977069
Inventors:
Jawad B. Khan - Cornelius OR, US
Ningde Xie - Hillsboro OR, US
Raj K. Ramanujan - Federal Way WA, US
Leena K. Puthiyedath - Beaverton OR, US
International Classification:
G06F 12/02
US Classification:
711103
Abstract:
An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.

Flexible Wear Management For Non-Volatile Memory

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US Patent:
20150309926, Oct 29, 2015
Filed:
May 6, 2015
Appl. No.:
14/705195
Inventors:
- Santa Clara CA, US
Robert W. Faber - Hillsboro OR, US
Ningde Xie - Hillsboro OR, US
International Classification:
G06F 12/02
Abstract:
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

Flexible Wear Management For Non-Volatile Memory

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US Patent:
20140143474, May 22, 2014
Filed:
Nov 21, 2012
Appl. No.:
13/682885
Inventors:
Prashant S. Damle - Portland OR, US
Robert W. Faber - Hillsboro OR, US
Ningde Xie - Hillsboro OR, US
International Classification:
G06F 12/02
US Classification:
711103
Abstract:
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.
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Ningde Xie from Portland, OR, age ~43 Get Report