Nidhi Aggarwal

7941698, May 10, 2011

Oct 15, 2008

12/252144

Nidhi Aggarwal - Sunnyvale CA, US
Norman Paul Jouppi - Palo Alto CA, US
Parthasarathy Ranganathan - Fremont CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 11/00

714 11, 714 10

Processor operating methods and integrated circuits are described. According to one embodiment, an integrated circuit includes a processor configured to execute a first application and to redundantly execute a second application while executing the first application, the first application being different from the second application. According to another embodiment, a processor operating method includes receiving a request to execute an application using a processor having a plurality of processor cores. The method also includes, in response to the receiving, determining whether the application should be executed redundantly or non-redundantly, non-redundantly executing the application using one processor core of the plurality if the determining comprises determining that the application should be executed non-redundantly, and redundantly executing the application using two or more processor cores of the plurality if the determining comprises determining that the application should be executed redundantly.

7966519, Jun 21, 2011

Oct 13, 2008

12/250381

Nidhi Aggarwal - Sunnyvale CA, US
Norman Paul Jouppi - Palo Alto CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 11/00

714 10, 712 15

Methods and integrated circuits for reconfiguration in a multi-core processor system with configurable isolation are described. According to one embodiment, a processor configuration method includes determining that a first module is faulty. A second module is configured to communicate with the first module when the first module is not faulty. The method also includes analyzing a third module with respect to a substitution criterion, selecting the third module based on the analyzing determining that the third module satisfies the substitution criterion, and subsequent to the selecting, configuring the second module to communicate with the third module instead of the first module. Additional embodiments are described in the disclosure.

8037350, Oct 11, 2011

Oct 13, 2008

12/250367

Nidhi Aggarwal - Sunnyvale CA, US
Norman Paul Jouppi - Palo Alto CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 11/00

714 11, 714 10, 718105

Processor operating methods and integrated circuits are described. According to one embodiment, a processor operating method includes executing an application using a first number of a plurality of processor cores. The method also includes, during the executing using the first number, evaluating a transition criterion and after the evaluating, executing the application using a second number of the plurality of processor cores. According to another embodiment, an integrated circuit includes a plurality of processor cores and processing circuitry. The processing circuitry is configured to configure a first number of the plurality of processor cores to execute an application, evaluate a transition criterion, and, in response to evaluating the transition criterion, configure a second number of the plurality of processor cores to execute the application. Additional embodiments are described in the disclosure.

8151122, Apr 3, 2012

Jul 5, 2007

11/773759

Parthasarathy Ranganathan - Fremont CA, US
Nidhi Aggarwal - Fremont CA, US
Norman Paul Jouppi - Palo Alto CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1/00

713300, 713310, 713324, 713340, 714 2, 714100

In a method for managing power budgets among a plurality of electronic components having respective power budgets, at least part of the power budget of an electronic component that has failed is dynamically re-allocated to at least one of the other plurality of electronic components, to thereby increase performance of the plurality of electronic components.

20110113208, May 12, 2011

May 1, 2008

12/989981

Norman Paul Jouppi - Palo Alto CA, US
Alan Lynn Davis - Coalville UT, US
Nidhi Aggarwal - Sunnyvale CA, US
Richard Kaufmann - San Diego CA, US

G06F 12/16
G06F 13/00

711162, 711E12103

Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory.

7743285, Jun 22, 2010

Apr 17, 2007

11/787881

Nidhi Aggarwal - Madison WI, US
Norman P. Jouppi - Palo Alto CA, US
Parthasarathy Ranganathan - Fremont CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 11/00

714 43

One embodiment relates to a high-availability computation apparatus including a chip multiprocessor. Multiple fault zones are configurable in the chip multiprocessor, each fault zone being logically independent from other fault zones. Comparison circuitry is configured to compare outputs from redundant processes run in parallel on the multiple fault zones. Another embodiment relates to a method of operating a high-availability system using a chip multiprocessor. A redundant computation is performed in parallel on multiple fault zones of the chip multiprocessor and outputs from the multiple fault zones are compared. When a miscompare is detected, an error recovery process is performed. Other embodiments, aspects and features are also disclosed.