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Neeraj Parik

from Los Gatos, CA
Age ~46
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Connected to:
Aashish G Parikh, 43Adam J Parikh, 32Akshay B Parikh, 65Alap G Parikh, 44Amit N Parikh, 65Anise V Parikh, 57Ansel Parikh, 33Arun D Parikh, 74Ashvin R Parikh, 74Bhumi D Parikh, 30

Neeraj Parik Phones & Addresses

  • Los Gatos, CA
  • 1135 Pembridge Dr, San Jose, CA 95118
  • Sunnyvale, CA
  • 3655 Pruneridge Ave, Santa Clara, CA 95051 (408) 244-3793
  • Cupertino, CA

Work

Company: Apple Oct 2012 Address: Cupertino, CA Position: Design engineer

Education

Degree: Master of Science School / High School: Stanford University 2004 to 2006 Specialities: Electrical Engineering

Skills

Fpga • Pcie • Asic • Soc • Computer Architecture • Compter Networks • Arm • Ddr3 • Axi • Serdes • Phy • Cache Coherency • Memory Controller • Ddr Calibration • Synthesis • Static Timing Analysis • Lpddr4 • Lpddr3 • Hbm • Ethernet Mac • Xilinx Tools • Amba Architecture • Spyglass • Fabric Interconnect • Pcs • Memory Subsystem Architecture • Ddr4 • Systemverilog • Perl • Verilog • Switching • Logic Equivalency Check • Formal Verification • Altera Quartus • Snoop Coherency Protocol • Directory Coherency Protocol • Machine Learning • Ace • Amba Ahb • Cortex • Xilinx Tools

Languages

English • Hindi

Industries

Semiconductors

Resumes

Resumes

Neeraj Parik Photo 1

Asics, Fpgas , Soft-Ips Micro-Architecture And Architecture

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Location:
1135 Pembridge Dr, San Jose, CA 95118
Industry:
Semiconductors
Work:
Apple - Cupertino, CA since Oct 2012
Design Engineer
Broadcom Jan 2008 - Oct 2012
Principal IC Design Engineer
Xilinx Inc Aug 2004 - Dec 2007
IP Design Engineer (FPGA)
GDA Technologies (acquired by Rambus Inc) Jun 2000 - Jul 2004
IC Design Engineer
Phlips Semiconductors May 1999 - May 2000
IC Design Engineer
Education:
Stanford University 2004 - 2006
Master of Science, Electrical Engineering Indian Institute of Technology, Delhi 1995 - 1999
Bachelor of Technology, Electrical Engineering
Skills:
Fpga
Pcie
Asic
Soc
Computer Architecture
Compter Networks
Arm
Ddr3
Axi
Serdes
Phy
Cache Coherency
Memory Controller
Ddr Calibration
Synthesis
Static Timing Analysis
Lpddr4
Lpddr3
Hbm
Ethernet Mac
Xilinx Tools
Amba Architecture
Spyglass
Fabric Interconnect
Pcs
Memory Subsystem Architecture
Ddr4
Systemverilog
Perl
Verilog
Switching
Logic Equivalency Check
Formal Verification
Altera Quartus
Snoop Coherency Protocol
Directory Coherency Protocol
Machine Learning
Ace
Amba Ahb
Cortex
Xilinx Tools
Languages:
English
Hindi

Publications

Us Patents

Reference Voltage Calibration Using A Qualified Weighted Average

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US Patent:
20190042492, Feb 7, 2019
Filed:
Jul 9, 2018
Appl. No.:
16/030794
Inventors:
- Cupertino CA, US
Brijesh Tripathi - Los Altos CA, US
Kiran Kattel - San Francisco CA, US
Rakesh L. Notani - Sunnyvale CA, US
Fabien S. Faure - Santa Clara CA, US
Sukalpa Biswas - Fremont CA, US
Kai Lun Hsiung - Fremont CA, US
Neeraj Parik - San Jose CA, US
Venkata Ramana Malladi - Santa Clara CA, US
Shiva Kumar - Mountain View CA, US
Chaitanya Polapragada - Fremont CA, US
Allen Kim - Belmont CA, US
International Classification:
G06F 13/16
Abstract:
An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Communication Queue Management System

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US Patent:
20180063016, Mar 1, 2018
Filed:
Aug 24, 2016
Appl. No.:
15/246046
Inventors:
- Cupertino CA, US
Christopher D. Shuler - Davis CA, US
Benjamin K. Dodge - San Jose CA, US
Thejasvi M. Vijayaraj - San Jose CA, US
Harshavardhan Kaushikkar - San Jose CA, US
Yang Yang - Mountain View CA, US
Rong Z. Hu - Saratoga CA, US
Srinivasa R. Sridharan - San Jose CA, US
Wolfgang H. Klingauf - San Jose CA, US
Neeraj Parik - San Jose CA, US
International Classification:
H04L 12/863
Abstract:
In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

System For Managing Memory Devices

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US Patent:
20180032281, Feb 1, 2018
Filed:
Aug 1, 2016
Appl. No.:
15/225343
Inventors:
- Cupertino CA, US
Peter F. Holland - Los Gatos CA, US
Erik P. Machnicki - Los Altos CA, US
Robert E. Jeter - Santa Clara CA, US
Rakesh L. Notani - Sunnyvale CA, US
Neeraj Parik - San Jose CA, US
Marc A. Schaub - Sunnyvale CA, US
International Classification:
G06F 3/06
G11C 11/406
Abstract:
In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Memory Interface System

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US Patent:
20160364345, Dec 15, 2016
Filed:
Jun 12, 2015
Appl. No.:
14/738265
Inventors:
- Cupertino CA, US
Neeraj Parik - San Jose CA, US
International Classification:
G06F 13/16
G11C 8/18
G11C 7/10
G06F 12/02
G06F 12/06
Abstract:
In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller. Additionally, in some embodiments, storing the configuration information may result in the configuration information being transmitted to the memory interface circuit more efficiently.

Reference Voltage Calibration Using A Qualified Weighted Average

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US Patent:
20160292094, Oct 6, 2016
Filed:
Apr 1, 2015
Appl. No.:
14/676174
Inventors:
- Cupertino CA, US
Brijesh Tripathi - Los Altos CA, US
Kiran Kattel - San Francisco CA, US
Rakesh L. Notani - Sunnyvale CA, US
Fabien S. Faure - Santa Clara CA, US
Sukalpa Biswas - Fremont CA, US
Kai Lun Hsiung - Fremont CA, US
Neeraj Parik - San Jose CA, US
Venkata Ramana Malladi - Santa Clara CA, US
Shiva Kumar - Mountain View CA, US
Chaitanya Polapragada - Fremont CA, US
Allen Kim - Belmont CA, US
International Classification:
G06F 13/16
Abstract:
An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Calibration Of Clock Signal For Data Transmission

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US Patent:
20160209866, Jul 21, 2016
Filed:
Jan 15, 2015
Appl. No.:
14/597321
Inventors:
- Cupertino CA, US
Neeraj Parik - San Jose CA, US
Sukalpa Biswas - Fremont CA, US
International Classification:
G06F 1/12
G06F 1/08
Abstract:
A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

System And Method Of Calibration Of Memory Interface During Low Power Operation

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US Patent:
20160034219, Feb 4, 2016
Filed:
Aug 4, 2014
Appl. No.:
14/450525
Inventors:
- Cupertino CA, US
Neeraj Parik - San Jose CA, US
Kai Lun Hsiung - Fremont CA, US
International Classification:
G06F 3/06
Abstract:
A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit.The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. The memory interface unit may be configured to operate in a normal mode and a low power mode. However, in response to an occurrence of a given predetermined interval while the memory interface unit is in the low power mode, the memory interface unit may be configured to calibrate the timing unit subsequent to transitioning to the normal mode.
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Neeraj Parik from Los Gatos, CA, age ~46 Get Report