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Naveen X Javarappa

from Portola Valley, CA
Age ~52
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Related to:
Vivek Sharma, 64Kusam Sharma, 58Javarappa S Kusuma, 57Anagh Sharma, 32
Connected to:
George B Javaras, 85John C Javaras, 76Kumar H Javarayappa, 55Andre Javardian, 70Tom G Javarinis, 61Joseph R Javate, 46Karen A Javate, 49Nestor I Javate, 65Mona N Javdan, 49Javid F Javdani, 59

Naveen Javarappa Phones & Addresses

  • Portola Valley, CA
  • San Jose, CA
  • 1672 Langport Dr, Sunnyvale, CA 94087
  • 686 Foxtail Dr, Sunnyvale, CA 94086 (408) 738-3632
  • 471 Acalanes Dr, Sunnyvale, CA 94086 (408) 738-3632
  • Mountain View, CA
  • Santa Clara, CA
  • Sanger, CA
  • Tempe, AZ

Resumes

Resumes

Naveen Javarappa Photo 1

Hardware Engineer

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Location:
1672 Langport Dr, Sunnyvale, CA 94087
Industry:
Semiconductors
Work:
Apple
Hardware Engineer
Pa Semi Oct 2004 - Jul 2008
Chip Design Engineer
Sun Microsystems Jul 1998 - Sep 2004
Senior Am Design Engineer
Medtronic Mar 1997 - Jun 1998
Co-Op
Education:
Arizona State University Aug 1996 - May 1998
Master of Science, Masters University of Mysore
Skills:
Circuit Design
Embedded Systems
Asic
Debugging
Languages:
English
Naveen Javarappa Photo 2

Engineer

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Location:
1672 Langport Dr, Sunnyvale, CA 94087
Industry:
Semiconductors
Work:
Pa Semi
Engineer

Publications

Us Patents

Level Shifter With Embedded Logic And Low Minimum Voltage

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US Patent:
8476930, Jul 2, 2013
Filed:
Jun 29, 2011
Appl. No.:
13/171781
Inventors:
Brian J. Campbell - Cupertino CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Naveen Javarappa - San Jose CA, US
Greg M. Hess - Mountain View CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03K 19/094
US Classification:
326 68
Abstract:
In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.

Multiplexer With Level Shifter

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US Patent:
8558603, Oct 15, 2013
Filed:
Dec 15, 2011
Appl. No.:
13/326932
Inventors:
Greg M. Hess - Mountain View CA, US
Naveen Javarappa - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03L 5/00
US Classification:
327333, 326 62, 326 81
Abstract:
A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.

Method And Apparatus For Power Domain Isolation During Power Down

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US Patent:
8570788, Oct 29, 2013
Filed:
Apr 27, 2011
Appl. No.:
13/095202
Inventors:
Greg M. Hess - Mountain View CA, US
Naveen Javarappa - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G11C 11/00
US Classification:
365154, 365226, 365227
Abstract:
An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain.

Level Shifter With Embedded Logic And Low Minimum Voltage

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US Patent:
7994820, Aug 9, 2011
Filed:
Oct 20, 2010
Appl. No.:
12/908574
Inventors:
Brian J. Campbell - Cupertino CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Naveen Javarappa - San Jose CA, US
Greg M. Hess - Mountain View CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03K 19/0175
US Classification:
326 68
Abstract:
In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.

Level Shifter With Embedded Logic And Low Minimum Voltage

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US Patent:
20090174458, Jul 9, 2009
Filed:
Mar 16, 2009
Appl. No.:
12/404597
Inventors:
Brian J. Campbell - Cupertino CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Naveen Javarappa - San Jose CA, US
Greg M. Hess - Mountain View CA, US
International Classification:
H03L 5/00
US Classification:
327333
Abstract:
In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.

Zero Keeper Circuit With Full Design-For-Test Coverage

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US Patent:
20140177354, Jun 26, 2014
Filed:
Dec 21, 2012
Appl. No.:
13/725784
Inventors:
- Cupertino CA, US
Greg M. Hess - Mountain View CA, US
Naveen Javarappa - San Jose CA, US
Assignee:
APPLE INC. - Cupertino CA
International Classification:
G11C 7/00
H03K 19/00
US Classification:
36518915, 326 16
Abstract:
A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.
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Naveen X Javarappa from Portola Valley, CA, age ~52 Get Report