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Navaneeth P Jamadagni

from Portland, OR
Age ~42
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Also known as:
Jamadagni Navaneeth
Related to:
Sandhya P Jamadagni, 39
Connected to:
Charmaine S Jamadar, 128Jamshed J Jamadar, 71Alejandro Jamaica, 35Burns Jamaica, 43Eduardo Jamaica, 51Jenny Jamaica, 47Kevin Jamaica, 51Lisa S Jamaica, 45Mario O Jamaica, 69Thompson Jamaica, 40

Navaneeth Jamadagni Phones & Addresses

  • Portland, OR
  • San Bruno, CA
  • South San Francisco, CA
  • San Francisco, CA
  • Daly City, CA
  • Foster City, CA
  • Redwood City, CA
  • Beaverton, OR

Work

Company: Oracle labs May 2013 Position: Research assistant

Education

School / High School: Portland State University- Portland, OR Jun 2014 Specialities: PhD in Electrical Engineering

Skills

Digital IC Design • Asynchronous Circuit Design • Computer Arithmetic •
Static Timing Analysis • Place and Route • Parasitic Extraction and Custom Layout.<... • IC Compiler • SoC Encounter • RTL Compiler • Electric • HSpice •
NanoSim • Calibre • StarRC and VCS.

Computer Langua... • TCL scripting • Verilog • VHDL • C++ • Knowledge of Java and
Shell scripting.

Resumes

Resumes

Navaneeth Jamadagni Photo 1

Senior Software Engineer

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Location:
Palo Alto, CA
Industry:
Computer Hardware
Work:
Asynchronous Research Center, Portland State University - Portland, Oregon Area since Apr 2010
Research Assistant
Oracle - Oracle Labs, Redwood Shores Jun 2011 - Sep 2012
Research Assistant
Portland State University 2006 - 2010
Student System Administrator
Portland State University Jun 2007 - Jun 2009
Teaching Assistant
Chemnitz University of Technology - Chemnitz, Germany Jun 2008 - Sep 2008
Research Intern
Education:
Portland State University 2010 - 2015
PhD, Electrical Engineering Visvesvaraya Technological University 2000 - 2004
Bachelor of Engineering, Telecommunications
Skills:
Vhdl
Computer Architecture
Integrated Circuit Design
Spice
Cadence Virtuoso
Python
Computer Arithmetic
Electric Vlsi Cad
Synopsys Tools
Static Timing Analysis
Place and Route
Parasitic Extraction
Verilog
Circuit Design
Algorithms
Simulations
Vlsi
C
C++
Programming
Linux
Matlab
Interests:
Education
Environment
Science and Technology
Animal Welfare
Arts and Culture
Health
Languages:
Kannada
Hindi
English
Navaneeth Jamadagni Photo 2

Research Assistant At Portland State University

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Position:
Research Assistant at Portland State University
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Portland State University since Mar 2010
Research Assistant
Office of Information Technology, Portland State University Oct 2006 - Mar 2010
Unix Student System Administrator
Portland State University Jun 2007 - Jun 2009
Teaching Assistant
Chemnitz University of Technology Jun 2008 - Sep 2008
Research Intern
Education:
Portland State University 2006 - 2010
MS, Electrical Engineering Visvesvaraya Technological University 2000 - 2004
BE, Telecommunication Engineering
Navaneeth Jamadagni Photo 3

Navaneeth Jamadagni Portland, OR

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Work:
Oracle Labs

May 2013 to 2000
Research Assistant
Asynchronous Research Center

Apr 2010 to 2000
Graduate Research Assistant
Portland State University
Portland, OR
Jun 2007 to Jun 2009
Graduate Teaching Assistant
Chemnitz Technical University

Jun 2008 to Sep 2008
Research Intern
Education:
Portland State University
Portland, OR
Jun 2014
PhD in Electrical Engineering
Portland State University
Portland, OR
Feb 2010
M.S in Electrical Engineering
Visvesvaraya Technological University
Belgaum, Karnataka
Jun 2004
B.E in Telecommunication Engineering
Skills:
Digital IC Design, Asynchronous Circuit Design, Computer Arithmetic,<br/>Static Timing Analysis, Place and Route, Parasitic Extraction and Custom Layout.<br/><br/>CAD Tools: Design Compiler, IC Compiler, SoC Encounter, RTL Compiler, Electric, HSpice,<br/>NanoSim, Calibre, StarRC and VCS.<br/><br/>Computer Languages: Python, TCL scripting, Verilog, VHDL, C++, Knowledge of Java and<br/>Shell scripting.

Publications

Us Patents

Performing A Division Operation Using A Split Division Circuit

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US Patent:
20140082036, Mar 20, 2014
Filed:
Mar 15, 2013
Appl. No.:
13/834869
Inventors:
Navaneeth P. Jamadagni - Portland OR, US
Ivan E. Sutherland - Portland OR, US
Assignee:
ORACLE INTERNATIONAL CORPORATION - Redwood City CA
International Classification:
G06F 7/48
US Classification:
708209, 708650, 708523
Abstract:
The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is optimized for a second range of divisor values; the first range is distinct from the second range. During operation, the circuit receives a divisor for the division operation. The circuit: determines whether the divisor is in the first range or the second range to determine whether the first divider or the second divider should perform the division operation; performs the division operation in the selected host divider; and then outputs the result that was generated by the selected host divider.

Performing Quotient Selection For A Carry-Save Division Operation

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US Patent:
20140082037, Mar 20, 2014
Filed:
Sep 17, 2013
Appl. No.:
14/028943
Inventors:
Navaneeth P. Jamadagni - Portland OR, US
Ivan E. Sutherland - Portland OR, US
Assignee:
Oracle International Corporation - Redwood City CA
International Classification:
G06F 7/64
US Classification:
708209
Abstract:
The disclosed embodiments disclose techniques for performing quotient selection in an iterative carry-save division operation that divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D. During a divide operation, a divider approximates Q by iteratively selecting an operation to perform for each iteration of the carry-save division operation and then performing the selected operation. The operation for each iteration is selected based on the current partial sum bits of a partial remainder in carry-save form (rs) and the current partial carry bits of a partial remainder in carry-save form (rc). More specifically, the operation is selected from a set of operations that includes: (1) a 2X* operation; (2) an S1 & 2X* operation; (3) an S2 & 2X* operation; (4) an A1 & 2X* operation; and (5) an A2 & 2X* operation.

Anomaly Detection Performance Enhancement Using Gradient-Based Feature Importance

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US Patent:
20230043993, Feb 9, 2023
Filed:
Aug 4, 2021
Appl. No.:
17/394193
Inventors:
- Redwood Shores CA, US
YUTING SUN - Bellevue WA, US
NAVANEETH JAMADAGNI - South San Francisco CA, US
FELIX SCHMIDT - Niederweningen, CH
MARIA VLACHOPOULOU - Bellevue WA, US
International Classification:
G06N 3/08
G06F 17/18
Abstract:
Herein are machine learning techniques that adjust reconstruction loss of a reconstructive model, such as a principal component analysis (PCA), based on importances of features. In an embodiment having a reconstructive model that more or less accurately reconstructs its input, a computer measures, for each feature, a respective importance that is based on the reconstructive model. For example, importance may be based on grading samples that the reconstructive model correctly or incorrectly inferenced. For each feature during production inferencing, a respective original loss from the reconstructive model measures a difference between a value of the feature in an input and a reconstructed value of the feature generated by the reconstructive model. For each feature, the respective importance of the feature is applied to the respective original loss to generate a respective weighted loss, which compensates for concept drift. The weighted losses of the features of the input are collectively detected as anomalous or non-anomalous.

Techniques For Accurately Estimating The Reliability Of Storage Systems

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US Patent:
20200371855, Nov 26, 2020
Filed:
May 13, 2020
Appl. No.:
15/930779
Inventors:
- Redwood Shores CA, US
Navaneeth Jamadagni - South San Francisco CA, US
Arun Raghavan - San Francisco CA, US
Craig Schelp - Vancouver, CA
Charles Gordon - Davis CA, US
International Classification:
G06F 11/07
Abstract:
Techniques are described herein for accurately measuring the reliability of storage systems. Rather than relying on a series of approximations, which may produce highly optimistic estimates, the techniques described herein use a failure distribution derived from a disk failure data set to derive reliability metrics such as mean time to data loss (MTTDL) and annual durability. A new framework for modeling storage system dynamics is described herein. The framework facilitates theoretical analysis of the reliability. The model described herein captures the complex structure of storage systems considering their configuration, dynamics, and operation. Given this model, a simulation-free analytical solution to the commonly used reliability metrics is derived. The model may also be used to analyze the long-term reliability behavior of storage systems.
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Navaneeth P Jamadagni from Portland, OR, age ~42 Get Report