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Nagendra Krishnapura Phones & Addresses

  • New York, NY
  • Jersey City, NJ
  • 1 John F Kennedy Blvd, Somerset, NJ 08873
  • 1146 Easton Ave, Somerset, NJ 08873 (732) 729-0341
  • 722 Willow Ave, Hoboken, NJ 07030 (201) 798-5250
  • Springfield, NJ

Publications

Us Patents

Glitch-Free Phase Switching Synthesizer

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US Patent:
6671341, Dec 30, 2003
Filed:
Sep 17, 1999
Appl. No.:
09/398371
Inventors:
Peter Kinget - Aliso Viejo CA
Nagendra Krishnapura - New York NY
Assignee:
Agere Systems, Inc. - Berkeley Heights NJ
International Classification:
H03D 324
US Classification:
375373, 375376
Abstract:
A system for generating a glitch-free output signal having a frequency. The system comprises a frequency divider for receiving a signal having an input frequency, wherein the frequency divider is configured to generate a plurality of corresponding phase-shifted signals. A retimer is coupled to the frequency divider and is configured to receive the phase-shifted signals and to generate multiplexer input signals for receipt by a multiplexer. The retimer is further configured to receive retimer control signals and to generate corresponding multiplexer control signals. The multiplexer is coupled to the retimer and has input terminals configured to receive the multiplexer input signals. The multiplexer is controlled by the multiplexer control signals so as to alternately and successively provide at its output terminal one of the multiplexer input signals. As the signal level of each phase-shifted signal transitions between a âhighâ position and a âlowâ position, the multiplexer control signals are configured to be employed at a time corresponding to the time when a phase-shifted signal experiences a transition.

Circuits With Dynamic Biasing

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US Patent:
6683492, Jan 27, 2004
Filed:
Jan 28, 2003
Appl. No.:
10/353199
Inventors:
Nagendra Krishnapura - Hoboken NJ
Yannis P. Tsividis - New York NY
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03B 100
US Classification:
327552
Abstract:
Techniques are provided for the implementation of dynamically biased circuits. In these circuits, bias currents are varied according to signal amplitude. Benefits include reduced power dissipation, reduced noise, and increased dynamic range. The techniques can be employed in various types of circuits such as, for example, amplifiers, log-domain circuits, and filters.

Circuits With Dynamic Biasing

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US Patent:
6717461, Apr 6, 2004
Filed:
Jan 28, 2003
Appl. No.:
10/353201
Inventors:
Nagendra Krishnapura - Hoboken NJ
Yannis P. Tsividis - New York NY
Assignee:
The Trustees of Columbia University in the City of New York - NY
International Classification:
H03B 100
US Classification:
327552
Abstract:
Techniques are provided for the implementation of dynamically biased circuits. In these circuits, bias currents are varied according to signal amplitude. Benefits include reduced power dissipation, reduced noise, and increased dynamic range. The techniques can be employed in various types of circuits such as, for example, amplifiers, log-domain circuits, and filters.

Circuits With Dynamic Biasing

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US Patent:
6816003, Nov 9, 2004
Filed:
Feb 5, 2001
Appl. No.:
09/777831
Inventors:
Nagendra Krishnapura - Hoboken NJ
Yannis P. Tsividis - New York NY
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03B 100
US Classification:
327552
Abstract:
Techniques are provided for the implementation of dynamically biased circuits. In these circuits, bias currents are varied according to signal amplitude. Benefits include reduced power dissipation, reduced noise, and increased dynamic range. The techniques can be employed in various types of circuits such as, for example, amplifiers, log-domain circuits, and filters.

Circuits With Dynamic Biasing

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US Patent:
6861896, Mar 1, 2005
Filed:
Jan 28, 2003
Appl. No.:
10/353200
Inventors:
Yannis P. Tsividis - New York NY, US
Nagendra Krishnapura - Hoboken NJ, US
Assignee:
The Trustees of Columbia University of the City of New York - New York NY
International Classification:
H03B001/00
US Classification:
327552
Abstract:
Techniques are provided for the implementation of dynamically biased circuits. In these circuits, bias currents are varied according to signal amplitude. Benefits include reduced power dissipation, reduced noise, and increased dynamic range. The techniques can be employed in various types of circuits such as, for example, amplifiers, log-domain circuits, and filters.

System And Method For Orthogonal Frequency Division Multiplexed Optical Communication

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US Patent:
7076169, Jul 11, 2006
Filed:
Feb 28, 2002
Appl. No.:
10/087022
Inventors:
Isaac Shpantzer - Bethesda MD, US
Yehouda Meiman - Rishon Letzion, IL
Michael Tseytlin - Bethesda MD, US
Olga Ritterbush - Rockville MD, US
Aviv Salamon - Washington DC, US
Peter Feldman - Short Hills NJ, US
Alper Demir - Istanbul, TR
Peter Kinget - Summit NJ, US
Nagendra Krishnapura - Hoboken NJ, US
Jaijeet Roychowdhury - Minneapolis MN, US
Assignee:
CeLight, Inc. - Silver Spring MD
International Classification:
H04J 14/06
H04J 4/00
H04B 10/00
H04B 10/04
H04B 10/06
US Classification:
398 76, 398 65, 398 74, 398152, 398163, 398184, 398185, 398205
Abstract:
A system for optical communication send optical signals over a plurality of wavelength channels. Each wavelength channel comprises a number of orthogonal subchannel frequencies which are spaced apart from one another by a predetermined amount. Each of the subchannel frequencies is modulated with data from a data stream. The data modulation scheme splits a subchannel frequency code into H and V components, and further processes the components prior to modulation with data. The various data-modulated subchannels are then combined into a single channel for transmission. The received signals are detected and demodulated with the help of a symbol timing recovery module which establishes the beginning and end of each symbol. A polarization mode distortion compensation module at the receiver is used to mitigate the effects to polarization more distortion in the fiber.

System And Method For Code Division Multiplexed Optical Communication

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US Patent:
7167651, Jan 23, 2007
Filed:
Sep 26, 2001
Appl. No.:
09/962243
Inventors:
Isaac Shpantzer - Bethesda MD, US
Michael Tseytlin - Bethesda MD, US
Yaakov Achiam - Rockville MD, US
Aviv Salamon - Washington DC, US
Israel Smilanski - Rockville MD, US
Olga Ritterbush - Rockville MD, US
Pak Shing Cho - Gaithersburg MD, US
Li Guoliang - North Potomac MD, US
Jacob Khurgin - Baltimore MD, US
Yehouda Meiman - Rishon Letzion, IL
Alper Demir - Jersey City NJ, US
Peter Feldman - Short Hills NJ, US
Peter Kinget - Summit NJ, US
Nagendra Krishnapura - Hoboken NJ, US
Jaijeet Roychowdhury - Minneapolis MN, US
Joseph Schwarzwalder - Gaithersburg MD, US
Charles Sciabarra - Ellicott City MD, US
Assignee:
CeLight, Inc. - Silver Spring MD
International Classification:
H04J 4/00
H04B 10/00
H04B 10/04
H04B 10/06
US Classification:
398 77, 398 74, 398152, 398184, 398205
Abstract:
A system for optical communication forms a family of orthogonal optical codes modulated by a data stream. The orthogonal codes are formed by creating a stream of evenly spaced-apart pulses using a pulse spreader circuit and modulating the pulses in amplitude and/or phase to form a family of orthogonal optical code words, each representing a symbol. A spreader calibration circuit is used to ensure accurate timing and modulation. Each code word is further modulated by a predetermined number of data bits. The data modulation scheme splits a code word into H and V components, and further processes the components prior to modulation with data, followed by recombining with a polarization beam combiner. The data-modulated code word is then sent, along with others to receiver. The received signal is detected and demodulated with the help of a symbol synchronization unit which establishes the beginning and end of the code words.

Programmable Frequency Divider

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US Patent:
62817213, Aug 28, 2001
Filed:
Feb 24, 2000
Appl. No.:
9/511987
Inventors:
Peter R. Kinget - Aliso Viejo CA
Nagendra Krishnapura - New York NY
Assignee:
Lucent Technologies, Inc. - Murray Hill NJ
International Classification:
H03K 2100
US Classification:
327115
Abstract:
We have recognized that the design and programming complexity associated with conventional frequency divider configurations can be significantly reduced by a configuration of functionally identical, modular division blocks which are each able to swallow at least one input cycle of a input signal by switching to a phase-lagging output once per output cycle. The number of input pulses swallowed when a division block switches to a lagging waveform is a direct function of the division block's location in the chain, such that the number of input cycles swallowed per phase switch increases moving down the chain of division blocks. Therefore, the chain of division blocks has discrete elements for achieving most-significant to least-significant division factor increments. The total number of input cycles swallowed by the chain of division blocks equals the sum of cycles swallowed by each division block. Thus, to achieve a variety of division factors, a controller controls which, if any, division blocks switch to a phase-lagging waveform once each output cycle.
Nagendra R Krishnapura from New York, NY, age ~50 Get Report