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Mysore P Divakar

from San Jose, CA
Age ~67
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Also known as:
Mysore Dr Divakar, Mysore Sowmya Divakar, Divakar Mysore
Phone and address:
1061 Big Sur Dr, San Jose, CA 95120
(408) 268-7497
Related to:
Daksha Divakar, 31Divakar Sowmya, 68Divakar Sowmya, 60
Connected to:
Adinarayana Divakaruni, 76Mohanan Divakaran, 75Ramana S Divakaruni, 63Sasikala D Divakaruni, 52Samuel S Divaker, 62Valerie Divalentin, 46Michael J Divalerio, 61Drew Divall, 79Megan R Divall, 39Dan A Divan, 66

Mysore Divakar Phones & Addresses

  • 1061 Big Sur Dr, San Jose, CA 95120 (408) 268-7497
  • 11296 Silver Buckle Way, San Diego, CA 92127 (858) 674-6854
  • 15267 Maturin Dr, San Diego, CA 92127 (858) 674-6854
  • El Segundo, CA
  • Venice, CA

Public records

Vehicle Records

Mysore Divakar

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Address:
1061 Big Sur Dr, San Jose, CA 95120
VIN:
JTDBT923071013542
Make:
TOYOTA
Model:
YARIS
Year:
2007

Publications

Us Patents

System And Method Of Reducing Die Attach Stress And Strain

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US Patent:
6946744, Sep 20, 2005
Filed:
Apr 24, 2003
Appl. No.:
10/423571
Inventors:
John Alan Maxwell - Newbury Park CA, US
Mysore Purushotham Divakar - San Diego CA, US
Assignee:
Power-One Limited
International Classification:
H01L023/48
US Classification:
257782, 257779, 257783, 257784, 257785, 257775
Abstract:
A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.

Dc-Dc Converter Implemented In A Land Grid Array Package

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US Patent:
7026664, Apr 11, 2006
Filed:
Apr 24, 2003
Appl. No.:
10/423603
Inventors:
Mysore Purushotham Divakar - San Jose CA, US
David Keating - Limerick, IE
Antoin Russell - Co. Limerick, IE
Assignee:
Power-One, Inc. - Camarillo CA
International Classification:
H01L 23/34
H01L 23/02
H01L 29/76
US Classification:
257107, 257133, 257698, 257341, 257343, 257401, 257728, 257725, 257724, 257773, 257706, 257786, 361760, 361768, 361720, 361712, 361783, 361767, 174252, 174262
Abstract:
A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Arrangement For Surface Mounting Of Subassemblies On A Mother Board

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US Patent:
7027305, Apr 11, 2006
Filed:
Nov 18, 2003
Appl. No.:
10/715907
Inventors:
David Keating - Limerick, IL
Antoin Russell - Limercik, IL
Mysore P. Divakar - San Jose CA, US
Thomas H. Templeton - Fremont CA, US
John Alan Maxwell - Newbury Park CA, US
Assignee:
Power-One, Inc. - Camarillo CA
International Classification:
H05K 7/20
US Classification:
361719, 361803, 361736, 439 65, 439 79, 439637
Abstract:
The invention provides arrangements to facilitate surface mounting of subassembly boards on a motherboard with reliable, high conductivity interconnection. In accordance with the invention, the subassembly interconnection arrangement is composed of separate power and sense connector arms formed on one or more base headers. The arrangement interconnects and supports the subassembly board on the motherboard surface. Each power arm advantageously comprises a plurality of split-based mounting lugs secured to the arm in a coplanar configuration. Each sense connector arm preferably comprises a plurality of connector pins secured to the arm in a coplanar configuration. Embodiments are disclosed for vertical and horizontal surface mounting.

Enhanced Connection Arrangement For Co-Planar Vertical Surface Mounting Of Subassemblies On A Mother Board

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US Patent:
7145085, Dec 5, 2006
Filed:
Oct 21, 2004
Appl. No.:
10/972488
Inventors:
David Keating - Limerick, IE
Antoin Russell - Limerick, IE
Mysore Purushotham Divakar - San Jose CA, US
Assignee:
Power One, Inc. - Grand Cayman
International Classification:
H05K 5/00
US Classification:
174520, 361788, 361786, 361741
Abstract:
The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By “vertically mounting” is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. Edge metallization of the subassembly board can provide enhanced thermal or electrical connection to the underlying portions of one or more lugs.

Pluggable Cable Connector

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US Patent:
8047865, Nov 1, 2011
Filed:
Jun 19, 2009
Appl. No.:
12/487778
Inventors:
Satish I. Patel - Roselle IL, US
Surendra Chitti Babu - Tinley Park IL, US
Mysore Purushotham Divakar - San Jose CA, US
Paul B. DuCharme - New Lenox IL, US
Paul W. Wachtel - Arlington Heights IL, US
Masud Bolouri-Saransar - Orland Park IL, US
David E. Urbasic - Chicago IL, US
Nicholas G. Martino - Crete IL, US
Ronald L. Tellas - Schereville IN, US
Assignee:
Panduit Corp. - Tinley Park IL
International Classification:
H01R 12/24
US Classification:
439499, 439466
Abstract:
A pair manager for use in securing a twin-axial cable to a printed circuit board is described. The pair manager comprises a generally block-shaped portion containing a pair of channels. The channels extend from the front face to the rear face of the block-shaped portion. An integral flange and a pair of integral fingers extend perpendicularly from the front face of the block-shaped portion. The flange extends generally from the center of the front face and the fingers extend from opposite edges of the front face. The fingers and flange function as a partial shield cavity around each pair of conductors. This design helps to maintain better impedance matching when connecting twin-axial cables to a printed circuit board.

Pluggable Cable Connector

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US Patent:
8172602, May 8, 2012
Filed:
Oct 28, 2011
Appl. No.:
13/283692
Inventors:
Satish I. Patel - Roselle IL, US
Surendra Chitti Babu - Tinley Park IL, US
Mysore Purushotham Divakar - San Jose CA, US
Paul B. DuCharme - New Lenox IL, US
Masud Bolouri-Saransar - Orland Park IL, US
Paul W. Wachtel - Arlington Heights IL, US
David E. Urbasic - Chicago IL, US
Nicholas G. Martino - Crete IL, US
Ronald L. Tellas - Schereville IN, US
Assignee:
Panduit Corp. - Tinley Park IL
International Classification:
H01R 12/24
US Classification:
439499
Abstract:
A pair manager for use in securing a twin-axial cable to a printed circuit board is described. The pair manager comprises a generally block-shaped portion containing a pair of channels. The channels extend from the front face to the rear face of the block-shaped portion. An integral flange and a pair of integral fingers extend perpendicularly from the front face of the block-shaped portion. The flange extends generally from the center of the front face and the fingers extend from opposite edges of the front face. The fingers and flange function as a partial shield cavity around each pair of conductors. This design helps to maintain better impedance matching when connecting twin-axial cables to a printed circuit board.

Pluggable Cable Connector

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US Patent:
8298002, Oct 30, 2012
Filed:
Apr 2, 2012
Appl. No.:
13/437377
Inventors:
Satish I. Patel - Roselle IL, US
Surendra Chitti Babu - Tinley Park IL, US
Mysore Purushotham Divakar - San Jose CA, US
Paul B. DuCharme - New Lenox IL, US
Masud Bolouri-Saransar - Orland Park IL, US
Paul W. Wachtel - Arlington Heights IL, US
David E. Urbasic - Chicago IL, US
Nicholas G. Martino - Crete IL, US
Ronald L. Tellas - Schererville IN, US
Assignee:
Panduit Corp. - Tinley Park IL
International Classification:
H01R 12/24
US Classification:
439499
Abstract:
A pair manager for use in securing a twin-axial cable to a printed circuit board is described. The pair manager comprises a generally block-shaped portion containing a pair of channels. The channels extend from the front face to the rear face of the block-shaped portion. An integral flange and a pair of integral fingers extend perpendicularly from the front face of the block-shaped portion. The flange extends generally from the center of the front face and the fingers extend from opposite edges of the front face. The fingers and flange function as a partial shield cavity around each pair of conductors. This design helps to maintain better impedance matching when connecting twin-axial cables to a printed circuit board.

Active Patch Panel

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US Patent:
8358508, Jan 22, 2013
Filed:
Mar 18, 2010
Appl. No.:
12/726412
Inventors:
Ronald A. Nordin - Naperville IL, US
Paul W. Wachtel - Arlington Heights IL, US
Masud Bolouri-Saransar - Orland Park IL, US
Robert D. Elliot - Naperville IL, US
Mysore Purushotham Divakar - San Jose CA, US
Surendra Chitti Babu - New Lenox IL, US
Assignee:
Panduit Corp. - Tinley Park IL
International Classification:
H05K 1/14
US Classification:
361737, 361720, 361748
Abstract:
An active patch panel uses small form factor plus (SFP+) connectivity with a plurality of channels extending between first and second faces of the panel. The channels connect ports on the opposing faces of the panel and are provided with additional electronic elements, such as an equalizer, a clock data recovery element, and a pre-emphasis element. A controller can be connected to the plurality of channels to provide instructions for simultaneous equalization and pre-emphasis of a plurality of cable assemblies in the same channel.
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Mysore P Divakar from San Jose, CA, age ~67 Get Report