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Moussadek Schlessel Belaidi

from Fishkill, NY
Age ~70
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Also known as:
Moussadek S Belaidi, Moussadek D Belaidi, Moe S Belaidi, Mossadek S Belaidi, Moussadek Schlessel, Mo Belaidi, Marisa Belaidi, Belaidi Moussadek, Belaidi Mo
Phone and address:
31 Hoose Blvd, Fishkill, NY 12524
(845) 896-3847
Related to:
Karen SchlesselKenneth C Schlessel, 98Marisa Belaidi, 37Ken C SchlesselSarah Belaidi, 39Kenneth C Schlessel, 94
Connected to:
Jawad Belaidi, 54Brent R Belair, 39Dusty L Belair, 50Jeffrey A Belair, 50Jennifer L Belair, 42Jennifer Belair, 36Josh M Belair, 48Kayla M Belair, 36Nicole E Belair, 41Philippe Belair, 56

Moussadek Belaidi Phones & Addresses

  • 31 Hoose Blvd, Fishkill, NY 12524 (845) 896-3847
  • Peekskill, NY
  • Newton Falls, OH
  • Lyndhurst, OH
  • Yorktown Hts, NY
  • Yorktown Hts, NY
  • 31 Hoose Blvd, Fishkill, NY 12524

Publications

Us Patents

Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
8006208, Aug 23, 2011
Filed:
May 18, 2010
Appl. No.:
12/781851
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716115, 716126
Abstract:
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Structure For An Integrated Circuit Design For Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
8032851, Oct 4, 2011
Filed:
Aug 28, 2007
Appl. No.:
11/845852
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Weil im Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716115, 716126, 716129, 716130
Abstract:
A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Routing Method For Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
20080148213, Jun 19, 2008
Filed:
Aug 27, 2007
Appl. No.:
11/845301
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Weil im Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
International Classification:
G06F 17/50
US Classification:
716 13
Abstract:
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Method, System, And Computer Program Product For Spare Circuitry Distribution

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US Patent:
20080301614, Dec 4, 2008
Filed:
Jun 4, 2007
Appl. No.:
11/757465
Inventors:
Eddy St. Juste - Bridgeport CT, US
Moussadek Belaidi - Fishkill NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 11
Abstract:
A method, system, and computer program product for spare circuitry distribution in an integrated circuit design are provided. The method includes receiving design data for the integrated circuit design. The design data includes descriptions of spare circuitry and physical area available for circuitry placement. The method further includes determining target placement locations for the spare circuitry, where the target placement locations create a balanced distribution of the spare circuitry throughout the physical area available for circuitry placement. The method also includes shifting the location of the spare circuitry from each target placement location towards a nearest clock block within the integrated circuit design, resulting in an updated integrated circuit design. The method additionally includes outputting the updated integrated circuit design.

Method, System, And Computer Program Product For Coupled Noise Timing Violation Avoidance In Detailed Routing

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US Patent:
20080313588, Dec 18, 2008
Filed:
Jun 13, 2007
Appl. No.:
11/762130
Inventors:
Markus Buehler - Schonbuch, DE
Moussadek Belaidi - Fishkill NY, US
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 6
Abstract:
A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.
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Moussadek Schlessel Belaidi from Fishkill, NY, age ~70 Get Report