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Mounir Youssef Bohsali

from Danville, CA
Age ~44
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Also known as:
Mounir Y Bohsali, Bohsali Mounir
Phone and address:
1027 Hill Meadow Pl, Danville, CA 94526
Related to:
Abir Nabil Bohsali, 44Lana BohsaliNajla Faroukyassin BohsaliBohsali AmroYoussef Bohsali Amro, 42
Connected to:
Charles J Bohse, 77Christopher Bohse, 95Ruben B Bohuchot, 76Beth A Bohun, 40Joshua J Bohuslavsky, 36Robert D Bohuslavicky, 77Allison Boi, 43Binh Boi, 50Luigi Boi, 104Tommy Boi, 82

Mounir Bohsali Phones & Addresses

  • 1027 Hill Meadow Pl, Danville, CA 94526
  • Alamo, CA
  • 1110 Jackson St, Albany, CA 94706 (510) 527-5477
  • Emeryville, CA
  • 181 Schooner Ct, Richmond, CA 94804 (510) 235-5861
  • Remsen, IA
  • Raleigh, NC
  • Durham, NC

Work

Company: Qualcomm Jan 2012 Position: Senior staff rf circuit design engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Berkeley 2001 to 2008 Specialities: Electrical Engineering

Skills

Circuit Design • Analog Circuit Design • Integrated Circuits

Industries

Computer Hardware

Resumes

Resumes

Mounir Bohsali Photo 1

Senior Staff Rf Circuit Design Engineer

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Qualcomm
Senior Staff Rf Circuit Design Engineer
National Semiconductor Jun 2006 - Jan 2012
Staff Circuit Design Engineer
Education:
University of California, Berkeley 2001 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Circuit Design
Analog Circuit Design
Integrated Circuits

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mounir Bohsali
Mbr
Lannoush, LLC
Custom Computer Programing · Custom Computer Programming Services, Nsk
1027 Hl Mdw Pl, Danville, CA 94526
Mounir Bohsali
Managing
Capital Management Systems, LLC
Investment Advisory & Capital/Portfolio
1110 Jackson St, Berkeley, CA 94706
Mounir Bohsali
Managing
Albohsali, LLC
Manufacturing Import Export Distribution
695 Glasgow Cir, Danville, CA 94526
32 N Jackson Way, Alamo, CA 94507

Publications

Us Patents

Oscillator For Providing Oscillation Signal With Controllable Frequency

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US Patent:
7863993, Jan 4, 2011
Filed:
Sep 8, 2008
Appl. No.:
12/206448
Inventors:
Mounir Bohsali - Albany CA, US
Ali Kiaei - Cupertino CA, US
Gerard Socci - Palo Alto CA, US
Masood Yousefi - Cupertino CA, US
Ali Djabbari - Saratoga CA, US
Ahmad Bahai - Lafayette CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03B 5/36
H03C 3/22
US Classification:
331116FE, 331 36 C, 331109, 331158, 331177 V
Abstract:
An oscillator, including amplifier circuitry and resonant circuitry, for providing an oscillation signal with a controllable frequency while maintaining a substantially constant steady state magnitude. Controllable reactive circuitry, included as part of the amplifier circuitry, has a reactance which can be controlled such that the resistive components of the amplifier circuitry and resonant circuitry impedances remain substantially equal. When in the form of serially coupled, controllable capacitances, the controllable reactive circuitry is controlled such that a ratio of changes in the controllable capacitances is approximately equal to a negative ratio of the capacitance values.

Spur Reduction Technique For Sampling Pll's

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US Patent:
8373481, Feb 12, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/973353
Inventors:
Xiang Gao - San Jose CA, US
Ahmad Bahai - Lafayette CA, US
Mounir Bohsali - Danville CA, US
Ali Djabbari - Saratoga CA, US
Eric Klumperink - Lichtenvoorde, NL
Bram Nauta - Borne, NL
Gerard Socci - Palo Alto CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/06
US Classification:
327159, 327149, 327158
Abstract:
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Low Power And Low Spur Sampling Pll

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US Patent:
8395427, Mar 12, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/973323
Inventors:
Xiang Gao - San Jose CA, US
Ahmad Bahai - Lafayette CA, US
Mounir Bohsali - Danville CA, US
Ali Djabbari - Saratoga CA, US
Eric Klumperink - Lichtenvoorde, NL
Bram Nauta - Enschede, NL
Gerard Socci - Palo Alto CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Sampling Phase Lock Loop (Pll) With Low Power Clock Buffer

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US Patent:
8427209, Apr 23, 2013
Filed:
Oct 17, 2012
Appl. No.:
13/654051
Inventors:
Ahmad Bahai - Lafayette CA, US
Mounir Bohsali - Alamo CA, US
Ali Djabbari - Saratoga CA, US
Eric Klumperink - Lichtenvoorde, NL
Bram Nauta - Enschede, NL
Gerard Socci - Palo Alto CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Phase-Locked Loop Including Sampling Phase Detector And Charge Pump With Pulse Width Control

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US Patent:
7737743, Jun 15, 2010
Filed:
Mar 7, 2008
Appl. No.:
12/044522
Inventors:
Xiang Gao - Enschede, NL
Eric A. M. Klumperink - Enschede, NL
Bram Nauta - Enschede, NL
Mounir Bohsali - Albany CA, US
Ali Kiaei - Santa Clara CA, US
Gerard Socci - Palo Alto CA, US
Ali Djabbari - Saratoga CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/06
US Classification:
327158, 327156, 327163, 375375, 375376
Abstract:
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Dual-Mode Amplification By Varying A Load Impedance

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US Patent:
20200007098, Jan 2, 2020
Filed:
Aug 28, 2018
Appl. No.:
16/115448
Inventors:
- San Diego CA, US
Ara Bicakci - Belmont CA, US
Haitao Gan - Santa Clara CA, US
Shen Wang - Palo Alto CA, US
Mounir Bohsali - Danville CA, US
Hedieh Elyasi - Santa Clara CA, US
Beomsup Kim - Los Altos Hills CA, US
International Classification:
H03F 3/217
H03F 1/02
H03F 3/21
H03F 3/68
Abstract:
An apparatus is disclosed for dual-mode amplification by varying a load impedance. In an example aspect, the apparatus includes a low-noise amplifier, a first component, a second component, and a switch. The first component has a first input impedance. The second component is coupled between the low-noise amplifier and the first component. The second component has a second input impedance that is greater than the first input impedance. The switch is coupled in parallel with the second component between the low-noise amplifier and the first component. The switch is configured to selectively be in an open state to engage the second component or a closed state to bypass the second component.

Dual-Band Low Noise Amplifier

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US Patent:
20160072456, Mar 10, 2016
Filed:
Sep 9, 2014
Appl. No.:
14/481251
Inventors:
- San Diego CA, US
Anup Savla - Santa Clara CA, US
Mounir Youssef Bohsali - Alamo CA, US
International Classification:
H03F 3/191
H03F 1/56
Abstract:
An apparatus includes amplification circuitry configured to amplify a radio frequency (RF) signal. The apparatus also includes differential inductors coupled to an output of the amplification circuitry. The differential inductors include a first inductor serially coupled to a second inductor, and the differential inductors are configured to filter the RF signal and to provide a differential output.
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Mounir Youssef Bohsali from Danville, CA, age ~44 Get Report