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Montray C Leavy

from Mendham, NJ
Age ~53
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Also known as:
Cantrell Leavy Montray, Montray C Levy, Leavy Montray
Related to:
Sally P Leavy, 57
Connected to:
Elaine S Leavy, 80Ethan R Leavy, 39Grace D Leavy, 80Jennifer M Leavy, 50Joshua Leavy, 45Leticia A Leavy, 63Pauline J Leavy, 38Sean Leavy, 54Tamara L Leavy, 57Tammy K Leavy, 56

Montray Leavy Phones & Addresses

  • Mendham, NJ
  • Denton, TX
  • 39 Fano St, Arcadia, CA 91006 (626) 294-9957
  • 39 Fano St #A, Arcadia, CA 91006
  • 8805 Falcon Crest Dr, McKinney, TX 75070 (214) 592-0034
  • Dallas, TX
  • Brookhaven, MS
  • Desoto, TX
  • Allen, TX
  • 39 Fano St #A, Arcadia, CA 91006 (626) 294-9957

Work

Company: Atmi Jul 2011 Address: Hsinchu, Taiwan Position: Field technology director, asia

Education

Degree: PhD School / High School: University of Mississippi 1993 to 1999 Specialities: Electrochemistry

Industries

Semiconductors

Resumes

Resumes

Montray Leavy Photo 1

Field Technology Director, Asia

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Position:
Field Technology Director, Asia at ATMI
Location:
Taiwan
Industry:
Semiconductors
Work:
ATMI - Hsinchu, Taiwan since Jul 2011
Field Technology Director, Asia
ATMI - Greater Los Angeles Area Jan 2010 - Jul 2011
Global Technology Manager, Copper Plating
Touchdown Technologies - Greater Los Angeles Area Jan 2009 - Jan 2010
Director Process Integration and Electroplating Technology
Touchdown Technologies - Greater Los Angeles Area Jun 2007 - Jan 2009
Electroplating Process Integration Manager
Texas Instruments - Dallas, TX Jun 2002 - Sep 2007
Member of Technical Staff
Education:
University of Mississippi 1993 - 1999
PhD, Electrochemistry University of Mississippi 1989 - 1993
BS, Chemistry

Business Records

Name / Title
Company / Classification
Phones & Addresses
Montray C. Leavy
Managing M, Managing
FAMILY FIRST REAL ESTATE SERVICES LLC
4121 Dundee Ln, Plano, TX 75093
8805 Falcon Crst Dr, McKinney, TX 75070

Publications

Us Patents

Single Mask Mim Capacitor And Resistor With In Trench Copper Drift Barrier

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US Patent:
7189615, Mar 13, 2007
Filed:
Jan 18, 2005
Appl. No.:
11/037530
Inventors:
Satyavolu Srinivas Papa Rao - Garland TX, US
Darius Lammont Crenshaw - Allen TX, US
Stephan Grunow - Dallas TX, US
Kenneth D. Brennan - Plano TX, US
Somit Joshi - Sunnyvale CA, US
Montray Leavy - McKinney TX, US
Phillip D. Matz - McKinney TX, US
Sameer Kumar Ajmera - Richardson TX, US
Yuri E. Solomentsev - Austin TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8242
US Classification:
438250, 438200, 438201
Abstract:
The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().

Contact Resistance Reduction By New Barrier Stack Process

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US Patent:
7256121, Aug 14, 2007
Filed:
Dec 2, 2004
Appl. No.:
11/002935
Inventors:
Duofeng Yue - Plano TX, US
Stephan Grunow - Dallas TX, US
Satyavolu S. Papa Rao - Garland TX, US
Noel M. Russell - Plano TX, US
Montray Leavy - McKinney TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/4763
US Classification:
438625, 438695, 257E21161, 257E2117, 257E21169
Abstract:
The present invention provides a method for forming an interconnect on a semiconductor substrate. The method includes forming an opening over an inner surface of the opening , the depositing forming a reentrant profile near a top portion of the opening. A portion of barrier is etched, which removes at least a portion of the barrier to reduce the reentrant profile. The etching also removes at least a portion of the barrier layer at the bottom of the opening.

Multi Material Secondary Metallization Scheme In Mems Fabrication

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US Patent:
8268156, Sep 18, 2012
Filed:
Dec 1, 2011
Appl. No.:
13/308545
Inventors:
Montray Leavy - Arcadia CA, US
Assignee:
Advantest America, Inc. - Cupertino CA
International Classification:
C25D 5/10
US Classification:
205170, 205220, 205223
Abstract:
Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.

Multi Material Secondary Metallization Scheme In Mems Fabrication

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US Patent:
8309382, Nov 13, 2012
Filed:
Oct 29, 2009
Appl. No.:
12/608873
Inventors:
Montray Leavy - Arcadia CA, US
Assignee:
Advantest America, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438 48, 257414, 257E21613, 257E29324, 216 52, 428577
Abstract:
Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.

Partial Plate Anneal Plate Process For Deposition Of Conductive Fill Material

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US Patent:
20060024962, Feb 2, 2006
Filed:
Jul 28, 2004
Appl. No.:
10/901857
Inventors:
Montray Leavy - McKinney TX, US
Stephan Grunow - Dallas TX, US
Satyavolu Papa Rao - Garland TX, US
Noel Russell - Plano TX, US
International Classification:
H01L 21/44
H01L 21/4763
US Classification:
438660000, 438638000, 438633000, 438631000, 438626000
Abstract:
A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (). One or more feature regions are formed in the interlayer dielectric layer (). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer ()). A first anneal is performed that promotes grain growth of the first conductive layer (). An additional conductive layer is formed on the first conductive layer () and an additional anneal is performed () that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device ().

Semiconductor Device Manufactured Using An Electrochemical Deposition Process For Copper Interconnects

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US Patent:
20080111237, May 15, 2008
Filed:
Nov 14, 2006
Appl. No.:
11/559495
Inventors:
Montray Cantrell Leavy - McKinney TX, US
Jeffrey Alan West - Dallas TX, US
Kyle James McPherson - Allen TX, US
Richard Allen Faust - Dallas TX, US
Lixin Wu - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/52
H01L 21/4763
US Classification:
257741, 438618, 257E21575, 257E23141
Abstract:
A method of manufacturing a semiconductor device that comprises forming an insulating layer over a semiconductive substrate and forming a copper interconnect. Forming the interconnect includes etching an interconnect opening in the insulating layer and filling the opening with copper plating. Filling with copper plating includes using a first and second ECD. An electrolyte solution of the first and second ECD contains organic additives, and a current of the first ECD is greater than a current of the second ECD.

Superfilling Secondary Metallization Process In Mems Fabrication

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US Patent:
20110100826, May 5, 2011
Filed:
Oct 29, 2009
Appl. No.:
12/608857
Inventors:
Montray Leavy - Arcadia CA, US
Assignee:
TOUCHDOWN TECHNOLOGIES, INC. - Cupertino CA
International Classification:
C25D 5/16
B44C 1/22
B32B 15/01
US Classification:
205 95, 216 52, 428577
Abstract:
Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and a sacrificial secondary metal that provides structural support for the primary metal component during machining More specifically, techniques are disclosed to increase the rate of secondary metal deposition between primary metal features in order to prevent voiding in the sacrificial secondary metal and thus enhance structural support of the primary metal during machining.
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Montray C Leavy from Mendham, NJ, age ~53 Get Report