Resumes
Resumes
Soc Physical Design And Integration
View pageLocation:
San Francisco, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Cadence Design Systems - San Jose since Apr 2013
AE (Physical Design)
Lattice Semiconductor Jul 2011 - Apr 2013
CAD Design Engineer
Open-Silicon Jan 2011 - Mar 2011
Intern Physical Design Engineer
AE (Physical Design)
Lattice Semiconductor Jul 2011 - Apr 2013
CAD Design Engineer
Open-Silicon Jan 2011 - Mar 2011
Intern Physical Design Engineer
Education:
California State University-Sacramento 2009 - 2011
M.S, Electrical Engineering
M.S, Electrical Engineering
Skills:
Tcl
Verilog
Vlsi
Asic
Eda
Physical Design
Cmos
Cadence Virtuoso
Soc
Drc
Static Timing Analysis
Rtl Design
Mixed Signal
Debugging
Semiconductors
Ir
Cadence Encounter
Verilog
Vlsi
Asic
Eda
Physical Design
Cmos
Cadence Virtuoso
Soc
Drc
Static Timing Analysis
Rtl Design
Mixed Signal
Debugging
Semiconductors
Ir
Cadence Encounter