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Mohammad Hekmat

from Portola Valley, CA
Age ~43
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Related to:
Sepideh Hekmat
Connected to:
Ahmed Hekmat, 64Elham Hekmat, 57Hormoz Hekmat, 89Jessica Hekmat, 39Yasaman Hekmat, 44Ali R Hekmatpour, 56Marcia A Hela, 70Larry R Helaas, 82Claudia J Helade, 78Luis A Helago, 59

Mohammad Hekmat Phones & Addresses

  • Portola Valley, CA
  • Sunnyvale, CA
  • Mountain View, CA
  • Stanford, CA

Resumes

Resumes

Mohammad Hekmat Photo 1

Senior Manager, Asic Design

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Location:
1422 Yukon Dr, Sunnyvale, CA 94087
Industry:
Consumer Electronics
Work:
Mojo Vision Inc. Aug 2017 - Jun 2019
Senior Staff Engineer
Mojo Vision Inc. Aug 2017 - Jun 2019
Senior Manager, Asic Design
Samsung Mar 2016 - Jul 2017
Senior Staff Engineer
Samsung Oct 2012 - Feb 2016
Staff Engineer
Rambus Jan 2011 - Oct 2012
Senior Member of Technical Staff - Circuit Design
Education:
Stanford University 2005 - 2010
Doctorates, Doctor of Philosophy, Electrical Engineering, Philosophy The University of British Columbia 2003 - 2005
Sharif University of Technology 1999 - 2003
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Analog Circuit Design
Circuit Design
Rf
Mixed Signal
Electrical Engineering
Asic
Cmos
Rf Circuits
Vlsi
Integrated Circuit Design
Semiconductors
Matlab
Low Power Design
Hardware Architecture
Embedded Systems
Cadence
Pll
Debugging
Engineering Management
Characterization
Pcb Design
Spice
Latex
Dfe
Cdr
Languages:
English
Persian
Mohammad Hekmat Photo 2

Senior Manager, Asic Design

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Location:
Sunnyvale, CA
Work:

Senior Manager, Asic Design
Mohammad Hekmat Photo 3

Mohammad Hekmat

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Mohammad Hekmat Photo 4

Student At Stanford University

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Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Education:
Stanford University 2005 - 2010

Publications

Us Patents

Integrated Circuit Comprising Fractional Clock Multiplication Circuitry

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US Patent:
20130135015, May 30, 2013
Filed:
Nov 27, 2012
Appl. No.:
13/686175
Inventors:
Masum Hossain - Sunnyvale CA, US
Farshid Aryanfar - Sunnyvale CA, US
Mohammad Hekmat - Mountain View CA, US
Reza Navid - San Francisco CA, US
International Classification:
H03B 19/00
US Classification:
327116
Abstract:
Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Methods And Circuits For Duty-Cycle Correction

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US Patent:
20130063191, Mar 14, 2013
Filed:
Sep 12, 2012
Appl. No.:
13/612540
Inventors:
Dinesh Patil - Sunnyvale CA, US
Mohammad Hekmat - Mountain View CA, US
Kambiz Kaviani - Palo Alto CA, US
Amir Amirkhany - Sunnyvale CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H03K 3/017
H03L 7/08
US Classification:
327156, 327175
Abstract:
A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.

Contact Lens Power Supply With Movable Generator

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US Patent:
20220221739, Jul 14, 2022
Filed:
Jan 8, 2021
Appl. No.:
17/145176
Inventors:
- Saratoga CA, US
Mohammad Hekmat - Sunnyvale CA, US
International Classification:
G02C 11/00
G02C 7/04
Abstract:
An electronic contact lens. In some embodiments, the electronic contact lens includes a plurality of power-consuming circuits and a power supply circuit. The power supply circuit may be configured to distribute available power among two voltage domains in the electronic contact lens according to changing power requirements within the two voltage domains.

Semiconductor Memory Systems With On-Die Data Buffering

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US Patent:
20210141748, May 13, 2021
Filed:
Oct 27, 2020
Appl. No.:
17/081909
Inventors:
- San Jose CA, US
Amir Amirkhany - Sunnyvale CA, US
Suresh Rajan - Fremont CA, US
Mohammad Hekmat - Mountain View CA, US
Dinesh Patil - Sunnyvale CA, US
International Classification:
G06F 13/16
G11C 7/10
G11C 8/18
G11C 11/419
G11C 7/22
G11C 11/4076
G11C 11/4093
G11C 11/4096
G11C 5/02
G06F 13/40
Abstract:
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Semiconductor Memory Systems With On-Die Data Buffering

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US Patent:
20200050561, Feb 13, 2020
Filed:
Aug 21, 2019
Appl. No.:
16/546694
Inventors:
- Sunnyvale CA, US
Amir Amirkhany - Sunnyvale CA, US
Suresh Rajan - Fremont CA, US
Mohammad Hekmat - Mountain View CA, US
Dinesh Patil - Sunnyvale CA, US
International Classification:
G06F 13/16
G06F 13/40
G11C 7/10
G11C 5/02
G11C 11/4096
G11C 11/4093
G11C 11/4076
G11C 7/22
G11C 11/419
G11C 8/18
Abstract:
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Method And Apparatus For Duty-Cycle Correction Of High Speed I/O

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US Patent:
20190272804, Sep 5, 2019
Filed:
Aug 7, 2018
Appl. No.:
16/057037
Inventors:
- Yongin-si, KR
Mohammad Hekmat - Sunnyvale CA, US
International Classification:
G09G 5/00
H03K 21/38
H03K 3/017
Abstract:
A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Hybrid Half/Quarter-Rate Dfe

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US Patent:
20190273639, Sep 5, 2019
Filed:
Aug 8, 2018
Appl. No.:
16/058896
Inventors:
- Yongin-si, KR
Amir Amirkhany - Sunnyvale CA, US
Mohammad Hekmat - Sunnyvale CA, US
International Classification:
H04L 25/03
H03K 3/356
Abstract:
A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Low Overhead On Chip Scope

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US Patent:
20190265278, Aug 29, 2019
Filed:
Aug 3, 2018
Appl. No.:
16/054609
Inventors:
- Yongin-si, KR
Mohammad Hekmat - Sunnyvale CA, US
Valentin Abramzon - Mountain View CA, US
Amir Amirkhany - Sunnyvale CA, US
International Classification:
G01R 13/02
H03M 3/00
H03M 1/06
H03F 3/387
H03F 3/45
H03M 1/12
Abstract:
An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.
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Mohammad Hekmat from Portola Valley, CA, age ~43 Get Report