Michael G Stephens

8456461, Jun 4, 2013

Apr 30, 2010

12/771526

Michael John Stephens - San Jose CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G09G 5/00

345207, 345 95, 345212

A method and apparatus for ambient light detection and power control using photovoltaics is disclosed. In an embodiment, a device includes a display and a photovoltaic cell. The photovoltaic cell acts as both an ambient light sensor and a power source. Based on the detected ambient light level, the brightness of the display is increased or decreased to save power, and energy captured by the photovoltaic cell is converted into a useable power signal which is stored or used by device components.

20010045848, Nov 29, 2001

Aug 4, 1998

09/128576

MICHAEL C. STEPHENS - SAN JOSE CA, US

H03L007/00

327/143000

A circuit for detecting when a derivative signal has reached its operating level during power-up of an integrated circuit includes a reset circuit, a latch circuit and a node monitoring circuit. The reset circuit, latch circuit and node monitoring circuit are all connected at a node. When power-up starts, the reset circuit causes the level at the node to be driven to an initial level corresponding to the level provided by an external power source. In response to this initial level at the node, the latch circuit generates an output signal with a level indicating that the derivative signal has not yet reached its operating level. The node monitoring circuit monitors the level of the derivative signal. When the level of the derivative signal reaches its operating level, the node monitoring circuit causes the level at the node to change so as to cause the latch circuit to generate the output signal with a level that indicates that the derivative signal has reached its operating level. The output signal is used to activate circuitry that uses the derivative signal as soon as the derivative signal has reached its operating level.

20080081616, Apr 3, 2008

Sep 30, 2006

11/537615

Wen Zhao - Cupertino CA, US
Arun G. Mathias - Sunnyvale CA, US
Felicia Tsu - Mountain View CA, US
Janell L. Paulson - Carlsbad CA, US
Michael J. Stephens - San Jose CA, US
Isabel Y. Mahe - Los Altos CA, US

H04Q 7/20

4554321

Techniques involving the acquisition of wireless communications systems are disclosed. For example, an apparatus may store a list of one or more preferred wireless communications systems. Upon identifying a first accessible wireless communications system that is absent from the list, the device may acquire this system. However, after this acquisition, the device may further identify a second accessible wireless communications system. If the second system is included in the list of one or more preferred wireless communications systems, the apparatus may acquire the second system.

55507832, Aug 27, 1996

Apr 19, 1995

8/424820

Michael C. Stephens - San Jose CA
Ajit K. Medhekar - San Jose CA

Alliance Semiconductor Corporation - San Jose CA

G11C 800

365233

A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).

62081977, Mar 27, 2001

Mar 4, 1999

9/262503

Luigi Ternullo - San Jose CA
Michael C. Stephens - San Jose CA

Vanguard International Semiconductor Corp. - Hsinchu

G05F1/10;2/02

327536

A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high. The logic circuit can also vary the voltage difference between the capacitor node and the external supply voltage to decrease the relative voltage level at the capacitor node relative to the level of the external supply voltage. These features also help reduce the risk of junction breakdown in the charge pump.

59994770, Dec 7, 1999

Jun 23, 1998

9/103676

Michael C. Stephens - San Jose CA

Vanguard International Semiconductor Corporation

G11C 800

36523003

An activation arrangement for reducing worst case localized supply noise for shared circuitry includes a first group of circuit blocks, a second group of circuit blocks, a shared circuit, and a selection circuit. The first and second circuit blocks are arranged symmetrically about the shared circuit. The selection circuit is configured to selectively activate each circuit block in the first group and, concurrently, a circuit block in the second group corresponding to the circuit block of the first group. The selection circuit is configured so that when the circuit block of the first group that is closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is farthest from the shared circuit. In a similar manner, the selection circuit is configured so that when the circuit block in the first group that is second closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is second farthest from the shared circuit, and so on.

55171370, May 14, 1996

May 19, 1995

8/445176

Michael C. Stephens - San Jose CA

Alliance Semiconductor Corporation - San Jose CA

H03K 1900

326 93

A self-timed synchronous clock pulse circuit (100) is disclosed that includes a pulse pull-down circuit (102) pulling a first pulse node (104) to ground upon receiving the rising edge of an external clock. A pulse generator (108) responsive to a high-to-low transition at the first pulse node (104) generates a second clock pulse. A pulse pull-up circuit (110) is responsive to the second edge of the second clock pulse and pulls the first pulse node (104) to the positive power supply. An initialization circuit (112) is provided to prevent a lock-up condition upon power-up by sampling the logic level of the first pulse node (104) on the rising edge of the external clock. The logic value is essentially held throughout the remainder of the clock cycle by gating the value into a second latch during the second portion of an external clock cycle. The sampled logic value is used to correct the lock-up condition by gating the logic level of the second latch (124) into a third latch (128) during a first portion of the external clock cycle, the output of the third latch (128) being coupled to an initialization pull-up circuit (114) which pulls the first pulse node (104) high such that within two clock cycles the power-up lock-up state is eliminated.

55505007, Aug 27, 1996

Jun 23, 1995

8/493901

Michael C. Stephens - San Jose CA
Ajit K. Medhekar - San Jose CA

Alliance Semiconductor Corporation - San Jose CA

H03K 513
H03K 5153

327261

A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.