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Miodrag M Potkonjak

from Los Angeles, CA
Age ~67
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Related to:
Nada M Potkonjak, 64Miroslav Aleksic
Connected to:
Mark L Potkovac, 60Susan M Potkul, 68Ajith K Potlapalli, 33Amy F Potler, 66Avinash Potluri, 43Kesava R Potluri, 78Padma Potluri, 51Rao B Potluri, 76Siva P Potluri, 39Sushma Potluri, 42

Miodrag Potkonjak Phones & Addresses

  • 715 Gayley Ave, Los Angeles, CA 90024 (310) 208-1085
  • 10968 Wilkins Ave, Los Angeles, CA 90024
  • 10982 Roebling Ave, Los Angeles, CA 90024 (310) 208-1085
  • Fremont, CA
  • Plainsboro, NJ

Resumes

Resumes

Miodrag Potkonjak Photo 1

Professor

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Location:
Los Angeles, CA
Work:
Ucla Computer Science Dept
Professor
Education:
University of California, Berkeley 1987 - 1991
Doctorates, Doctor of Philosophy, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science University of California
Miodrag Potkonjak Photo 2

Miodrag Potkonjak

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Miodrag Potkonjak Photo 3

Miodrag Potkonjak

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Location:
Greater Los Angeles Area
Industry:
Higher Education

Business Records

Name / Title
Company / Classification
Phones & Addresses
Miodrag Potkonjak
Aristaeus Hermes, LLC
Creation and Management of Intellectual · Business Services at Non-Commercial Site · Nonclassifiable Establishments
715 Gayley Ave, Los Angeles, CA 90024
10968 Wilkins Ave, Los Angeles, CA 90024

Publications

Us Patents

Multi-Resolution Viterbi Decoding Technique

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US Patent:
6948114, Sep 20, 2005
Filed:
Apr 25, 2002
Appl. No.:
10/132360
Inventors:
Miodrag Potkonjak - Fremont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Dusan Petranovic - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03M013/03
US Classification:
714792, 714796
Abstract:
A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.

Methods And Systems For The Identification Of Circuits And Circuit Designs

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US Patent:
7017043, Mar 21, 2006
Filed:
Mar 20, 2000
Appl. No.:
09/528522
Inventors:
Miodrag Potkonjak - Los Angeles CA, US
Assignee:
The Regents of the University of California - Oakland CA
International Classification:
H04L 9/00
G06F 9/45
US Classification:
713176, 713181, 726 32, 716 10
Abstract:
The present invention is related to systems and methods for adding a signature to circuit design. In one embodiment, a first set of constraints used to specify a functional portion of the circuit design is received. A second set of constraints used to specify the signature is received as well. The circuit design is generated based on at least the first constraints and the second constraints, wherein the signature is embedded in the functional portion.

Decoder Using A Memory For Storing State Metrics Implementing A Decoder Trellis

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US Patent:
7467359, Dec 16, 2008
Filed:
Nov 3, 2005
Appl. No.:
11/266687
Inventors:
Miodrag Potkonjak - Fremont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Dusan Petranovic - Cupertino CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
H03M 13/03
US Classification:
716 1, 716 4, 714792, 714795, 714799
Abstract:
A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Lightweight Secure Physically Unclonable Functions

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US Patent:
7898283, Mar 1, 2011
Filed:
Aug 31, 2009
Appl. No.:
12/551209
Inventors:
Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US
International Classification:
H03K 19/00
US Classification:
326 8, 326 47
Abstract:
Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Decoder Using A Memory For Storing State Metrics Implementing A Decoder Trellis

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US Patent:
7900184, Mar 1, 2011
Filed:
Dec 16, 2008
Appl. No.:
12/336104
Inventors:
Miodrag Potkonjak - Fremont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Dusan Petranovic - Cupertino CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
G06F 11/22
H03M 13/03
US Classification:
716136, 716100, 714792, 714795, 714799
Abstract:
A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Input Compensated And/Or Overcompensated Computing

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US Patent:
8041992, Oct 18, 2011
Filed:
May 11, 2009
Appl. No.:
12/463982
Inventors:
Miodrag Potkonjak - Los Angeles CA, US
Assignee:
Technology Currents LLC - Wilmington DE
International Classification:
G06F 11/00
US Classification:
714 10
Abstract:
Techniques are generally described for correcting computation errors via input compensation and/or input overcompensation. In various examples, errors of a computation may be detected, and input compensation and/or overcompensation to correct the errors may be created. The disclosed techniques may be used for power and/or energy minimization/reduction, and debugging, among other applications. Other embodiments and/or applications may be disclosed and/or claimed.

Lightweight Secure Physically Unclonable Functions

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US Patent:
8054098, Nov 8, 2011
Filed:
Jan 4, 2011
Appl. No.:
12/984275
Inventors:
Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US
Assignee:
Empire Technology Development LLC - Wilmington DE
International Classification:
H03K 19/00
US Classification:
326 8, 326 47
Abstract:
Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Network Node Location Discovery

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US Patent:
8054762, Nov 8, 2011
Filed:
Mar 31, 2009
Appl. No.:
12/415523
Inventors:
Miodrag Potkonjak - Los Angeles CA, US
Assignee:
Technology Currents LLC - Wilmington DE
International Classification:
H04L 12/28
H04W 4/00
G06F 15/173
US Classification:
370254, 370328, 370338, 709223
Abstract:
Techniques are generally described for determining locations of a number of communication devices in a network. A method for determining locations of a number of communication devices in a network may include one or more of solving an objective function to determine a first set of locations of one or more of the number of communication devices. The method may further include re-solving either the objective function or a modified variant of the objective function, to determine a second set of locations of the communication devices; comparing the first set of locations with the second set of locations; and determining the locations of the communication devices based at least in part on the comparing.
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Miodrag M Potkonjak from Los Angeles, CA, age ~67 Get Report