Minru Lee

49336428, Jun 12, 1990

Feb 17, 1989

7/312691

Minru Lee - San Jose CA

Linear Technology Corporation - Milpitas CA

H03F 102
H03F 114

330 9

A CMOS chopper-stabilized operational amplifier including a nulling amplifier and a main amplifier has a pair of two input differential amplifiers in the input stage of each of the nulling amplifier and the main amplifier. In the nulling amplifier, one two-input differential amplifier switchably receives the input signals to the chopper stabilized operational amplifier, while the other two input differential amplifier functions in a feedback loop for developing a nulling voltage for the DC offset of the first two input differential amplifier. The operational amplifier has a three-phase clock and samples through a nulling time period, a setting time period, and a sampling time period.

49821164, Jan 1, 1991

Dec 26, 1989

7/457157

Minru Lee - San Jose CA

Linear Technology Corporation - Milpitas CA

H03K 3027
H03K 1704

307480

A clock selection circuit having a single input terminal for receiving an external clock signal and including logic means for selectively passing an external clock signal and an internal clock signal to an output. A clock detector is connected to the input terminal for generating a voltage in response to an external clock signal. The generated voltage is utilized in controlling the logic circuitry in selectively passing the external clock signal or the internal clock signal. In a preferred embodiment, the logic circuitry includes a first two input NAND gate, a second two input NAND gate, and a third two input NAND gate. One input of the first NAND gate receives the external clock signal, and one input to the second NAND gate receive sthe internal clock. The two outputs of the first and second NAND gates are connected to the inputs of the third NAND gate. The output from the clock detector is connected to the other input of the first NAND gate and is connected through an inverter to the other input of the second NAND gate.