Ming Sun

7202113, Apr 10, 2007

Jun 9, 2005

11/149954

Ming Sun - Sunnyvale CA, US
Demei Gong - Shanghai, CN

H01L 21/00

438123, 438111, 438119, 438613, 257E2304, 257E2302, 257E23046, 257E23053

A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.

7394151, Jul 1, 2008

Feb 15, 2005

11/058913

Leeshawn Luo - Santa Clara CA, US
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US
Xiao Tian Zhang - San Jose CA, US

Alpha & Omega Semiconductor Limited - Sunnyvale CA

H01L 23/48

257690, 257693, 257E21511

A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

7466014, Dec 16, 2008

Apr 9, 2007

11/786045

Ming Sun - Sunnyvale CA, US
Demei Gong - Shanghai, CH

H01L 23/495

257673, 257666, 257676, 438108, 438613

A flip chip mounted semiconductor device package having a dimpled leadframe is disclosed. The semiconductor device package includes a leadframe having a plurality of source dimples and a gate dimple, and a semiconductor die having a plurality of source contact areas and a gate contact area corresponding to the leadframe source dimples and gate dimple respectively, the semiconductor die being flipped onto the leadframe such that cured conductive epoxy provides electrical and mechanical contact between the plurality of source contact areas and the plurality of source dimples, and the gate contact area and the gate dimple.

7511361, Mar 31, 2009

Jun 10, 2005

11/150489

Xiaotian Zhang - San Jose CA, US
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US

H01L 23/495

257666, 257787, 257E23031

A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.

7612439, Nov 3, 2009

Dec 22, 2005

11/316614

Xiaotian Zhang - San Jose CA, US
Argo Chang - Taipei, TW
James Lee - Taipei, TW
Ryan Huang - Taipei, TW
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US

Alpha and Omega Semiconductor Limited - Hamilton

H01L 23/495
H01L 23/48

257676, 257E23037, 257E23044, 257E23069, 257E23071, 257E23178, 257666, 257686, 257685, 257724, 257723, 257691, 257698, 257696, 257773, 257341

A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

7622796, Nov 24, 2009

Sep 28, 2007

11/906136

Lei Shi - Shanghai, CN
Ming Sun - Sunnyvale CA, US
Kai Liu - Mountain View CA, US

Alpha and Omega Semiconductor Limited - Sunnyvale CA

H01L 23/02

257678, 257341, 257401, 257522, 257579, 257587, 257692, 257735, 257E21451, 257E29318

A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

7659191, Feb 9, 2010

Nov 27, 2006

11/605831

Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/00
H01L 21/76
H01L 21/30
H01L 21/46
H01L 21/44

438611, 438118, 438406, 438459, 257E21514, 257E21596

A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

7683464, Mar 23, 2010

Apr 30, 2007

11/799467

Ming Sun - Sunnyvale CA, US
Lei Shi - Shanghai, CN
Kai Liu - Mountain View CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 23/495

257666, 257692

A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.