Ming Hsien Limas Lin

6855982, Feb 15, 2005

Feb 2, 2004

10/770163

Qi Xiang - San Jose CA, US
James N. Pan - Fishkill NY, US
Ming Ren Lin - Cupertino CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H11L029/76

257330, 257 59, 438259, 438270, 438271, 438589

A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.

6893929, May 17, 2005

Aug 15, 2003

10/641548

Qi Xiang - San Jose CA, US
Ming Ren Lin - Cupertino CA, US
Minh V. Ngo - Fremont CA, US
Haihong Wang - Fremont CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L021/336

438303, 438933

The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

6924182, Aug 2, 2005

Aug 15, 2003

10/642375

Qi Xiang - San Jose CA, US
Ming Ren Lin - Cupertino CA, US
Minh V. Ngo - Fremont CA, US
Eric N. Paton - Morgan Hill CA, US
Haihong Wang - Fremont CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L021/8234
H01L021/76

438197, 438424

The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

6943087, Sep 13, 2005

Dec 17, 2003

10/738529

Qi Xiang - San Jose CA, US
Jung-Suk Goo - Stanford CA, US
James N. Pan - Fishkill NY, US
Ming Ren Lin - Cupertino CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L021/331
H01L021/8222

438311, 438149, 438183

Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.

7001837, Feb 21, 2006

Jan 17, 2003

10/346617

Minh V. Ngo - Fremont CA, US
Paul R. Besser - Sunnyvale CA, US
Ming Ren Lin - Cupertino CA, US
Haihong Wang - Fremont CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21/4763

438634, 438585, 438595, 438197, 438230, 438618, 438933

An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

7514958, Apr 7, 2009

Oct 16, 2007

11/872831

Yingjie Zhou - San Diego CA, US
Ming Lin - Tustin CA, US
Nathan Le - Gilbert AZ, US
Mitchell Buznitsky - Carlsbad CA, US
Yuqian C. Wong - San Diego CA, US
Craig Stein - Rancho Santa Margarita CA, US

Broadcom Corporation - Irvine CA

H03K 19/177

326 38, 326 33, 326136

In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource.

7701019, Apr 20, 2010

Feb 17, 2006

11/356606

Minh V. Ngo - Fremont CA, US
Paul R. Besser - Sunnyvale CA, US
Ming Ren Lin - Cupertino CA, US
Haihong Wang - Fremont CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 27/088

257401, 257206, 257204, 257900, 438197, 438230, 438634, 438585, 438595

An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

8180308, May 15, 2012

Feb 18, 2009

12/372858

Sek Kin Neng - San Jose CA, US
Yungping Hsu - Saratoga CA, US
Tsunglun Yu - Cupertino CA, US
Ming Ta Lin - San Jose CA, US
Naveen-Kumar Arani - Santa Clara CA, US

Marvell International Ltd. - Hamilton

H04B 17/00

4552262, 4552321, 4552511

A communication apparatus includes a radio frequency (RF) apparatus. The RF apparatus includes an amplifier, and a signal detection circuit. The amplifier receives RF signals and amplifies those signals. The amplifier has an adjustable gain value. The signal detection circuit detects whether a received signal is an out-of-band radar signal depending on the gain value of the amplifier and a characteristic of the received signal.