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Milind Jayram Gadre

from San Jose, CA
Age ~38
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Also known as:
Milind J Gadre, Gadre Milind
Connected to:
Aditi Gadre, 42Anuprita Gadre, 37Kaustubh S Gadre, 50Makarand A Gadre, 80Rajesh Gadre, 54Rucha R Gadre, 27Vaishali A Gadre, 52Jessica M Gadreau, 44Kevin L Gadreault, 60Eric C Gadrix, 55

Milind Gadre Phones & Addresses

  • San Jose, CA
  • Los Altos, CA
  • Santa Clara, CA
  • Sunnyvale, CA
  • Madison, WI
  • Brookline, MA

Work

Company: University of wisconsin-madison - Madison, WI Aug 2009 Position: Graduate assistant

Education

School / High School: University of Wisconsin-Madison- Madison, WI Aug 2014 Specialities: Ph.D. in Materials Science

Resumes

Resumes

Milind Gadre Photo 1

Milind Gadre Madison, WI

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Work:
University of Wisconsin-Madison
Madison, WI
Aug 2009 to Aug 2014
Graduate Assistant
Massachusetts Institute of Technology
Cambridge, MA
Mar 2013 to May 2013
Graduate Intern
Computational Materials Group
Madison, WI
2009 to 2012
System Administrator
Materials Science & Engineering
Madison, WI
Mar 2010 to May 2010
La/Sr
Larsen and Toubro Ltd
Mumbai, Maharashtra
Jun 2008 to Aug 2008
Technical Project Trainee
Undergraduate UROP, Metallurgical Engineering & Materials Science
Mumbai, Maharashtra
Mar 2008 to May 2008
Ceramic gel-casting method-development for Rapid Prototyping
Education:
University of Wisconsin-Madison
Madison, WI
Aug 2014
Ph.D. in Materials Science
Indian Institute of Technology Bombay
Mumbai, Maharashtra
Aug 2005 to May 2009
B.Tech. in Metallurgical Engineering and Materials Science

Publications

Us Patents

Deposition Of Metal Silicide Layers On Substrates And Chamber Components

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US Patent:
20200357643, Nov 12, 2020
Filed:
Jul 29, 2020
Appl. No.:
16/942171
Inventors:
- Santa Clara CA, US
Jiarui WANG - San Jose CA, US
Kwangduk Douglas LEE - Redwood City CA, US
Milind GADRE - Los Altos CA, US
Xiaoquan MIN - Mountain View CA, US
Paul CONNORS - San Mateo CA, US
International Classification:
H01L 21/225
C23C 16/24
C23C 16/42
G03F 1/38
H01L 21/033
C23C 16/455
Abstract:
Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

Substrate Deformation Detection And Correction

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US Patent:
20200357672, Nov 12, 2020
Filed:
Jul 29, 2020
Appl. No.:
16/942469
Inventors:
- Santa Clara CA, US
Milind GADRE - Los Altos CA, US
International Classification:
H01L 21/67
H01J 37/32
Abstract:
A method and apparatus for detecting and correcting incoming substrate deformation is disclosed. Substrates are positioned in a first process chamber, where the presence and type of substrate bow is detected. Based upon the detection of substrate bow, and a determination of whether the substrate has a compressive bow or a tensile bow, a substrate processing program is selected for execution. The substrate processing program can be executed in the first process chamber or in a second process chamber to correct or alleviate the bow prior to or during further processing of the substrate.

Substrate Deformation Detection And Correction

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US Patent:
20190341285, Nov 7, 2019
Filed:
Apr 5, 2019
Appl. No.:
16/377010
Inventors:
- Santa Clara CA, US
Milind GADRE - Los Altos CA, US
International Classification:
H01L 21/67
H01J 37/32
Abstract:
A method and apparatus for detecting and correcting incoming substrate deformation is disclosed. Substrates are positioned in a first process chamber, where the presence and type of substrate bow is detected. Based upon the detection of substrate bow, and a determination of whether the substrate has a compressive bow or a tensile bow, a substrate processing program is selected for execution. The substrate processing program can be executed in the first process chamber or in a second process chamber to correct or alleviate the bow prior to or during further processing of the substrate.

Oxide With Higher Utilization And Lower Cost

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US Patent:
20190074176, Mar 7, 2019
Filed:
Sep 4, 2018
Appl. No.:
16/120867
Inventors:
- Santa Clara CA, US
Praket P. JHA - San Jose CA, US
Milind GADRE - Los Altos CA, US
Deenesh PADHI - Sunnyvale CA, US
International Classification:
H01L 21/02
C23C 16/40
C23C 16/50
Abstract:
Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.

Deposition Of Metal Silicide Layers On Substrates And Chamber Components

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US Patent:
20180330951, Nov 15, 2018
Filed:
May 11, 2018
Appl. No.:
15/977388
Inventors:
- Santa Clara CA, US
Jiarui WANG - San Jose CA, US
Kwangduk Douglas LEE - Redwood City CA, US
Milind GADRE - Santa Clara CA, US
Xiaoquan MIN - Mountain View CA, US
Paul CONNORS - San Mateo CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/225
G03F 1/38
Abstract:
Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

Borane Mediated Dehydrogenation Process From Silane And Alkylsilane Species For Spacer And Hardmask Application

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US Patent:
20180076042, Mar 15, 2018
Filed:
Sep 5, 2017
Appl. No.:
15/695269
Inventors:
- Santa Clara CA, US
Ziqing DUAN - Sunnyvale CA, US
Milind GADRE - Santa Clara CA, US
Praket P. JHA - San Jose CA, US
Abhijit Basu MALLICK - Fremont CA, US
Deenesh PADHI - Sunnyvale CA, US
International Classification:
H01L 21/285
H01L 21/3205
H01L 21/02
H01L 21/3105
C23C 16/30
Abstract:
Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.

Self-Centering Pedestal Heater

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US Patent:
20170353994, Dec 7, 2017
Filed:
Jun 6, 2016
Appl. No.:
15/174526
Inventors:
- Santa Clara CA, US
Yuxing ZHANG - Santa Clara CA, US
Milind GADRE - Santa Clara CA, US
Sanjeev BALUJA - Campbell CA, US
International Classification:
H05B 1/02
H05B 3/24
Abstract:
A pedestal is provided that includes a body, a heater embedded in the body, a support pocket formed within the body having a surface disposed in a first plane, a peripheral surface disposed in a second plane surrounding the support pocket, and a plurality of centering tabs positioned between the support pocket and the peripheral surface, each of the centering tabs having a surface disposed in a third plane that is between both of the first and second planes.
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Milind Jayram Gadre from San Jose, CA, age ~38 Get Report