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Mihran H Touriguian

from Hercules, CA
Age ~60
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Also known as:
Mihran N
Phone and address:
2 Moonstone Ct, Rodeo, CA 94547
(510) 799-1364
Related to:
Raffi Touriguian
Connected to:
Fredda R Tourin, 76David Touring, 69Johnny P Tourino, 70Maria D Tourino, 64Lambros J Touris, 79Brian T Tourish, 68Kathleen A Tourison, 73Tanya Tourison, 49Joseph Tourissa, 41Roxanne Tourkay, 35

Mihran Touriguian Phones & Addresses

  • 2 Moonstone Ct, Hercules, CA 94547 (510) 799-1364
  • El Cerrito, CA
  • Santa Clara, CA
  • 2 Moonstone Ct, Hercules, CA 94547 (530) 743-7136

Work

Position: Handlers, Equipment Cleaners, Helpers, and Laborers Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Mihran Touriguian Photo 1

Mihran Touriguian

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Mihran Touriguian Photo 2

Experienced Dsp Engineering In Communications

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Position:
Senior DSP Software Engineer at BDTI
Location:
San Francisco Bay Area
Industry:
Wireless
Work:
BDTI since Nov 2007
Senior DSP Software Engineer
Atmel Corporation Jan 2005 - Apr 2007
Staff Engineer, Digital Signal Processing
Seda Solutions Apr 2003 - Jan 2005
System Engineer
Self-employed Nov 2000 - Mar 2003
Consultant
Systemonics Mar 2000 - Oct 2000
System Design Engineer
Education:
Purdue University 1983 - 1988
MS, Electrical and Computer Engineering
Skills:
Digital Signal Processors
WCDMA
Wireless
Embedded Systems
Embedded Software
ASIC
RF
Digital Signal Processing
GSM
Algorithms
Mobile Communications
Testing
RTL design
H.264
System Design
Hardware
Edge
Signal Processing
ARM
Debugging
SoC
3GPP
Languages:
French
Arabic
Armenian
Italian

Publications

Us Patents

Digital Signal Processor Optimized For Decoding A Signal Encoded In Accordance With A Viterbi Algorithm

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US Patent:
56338970, May 27, 1997
Filed:
Nov 16, 1995
Appl. No.:
8/558745
Inventors:
Gerhard P. Fettweis - Dresden, DE
Mihran Touriguian - Hercules CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H03D 100
H04L 2706
US Classification:
375341
Abstract:
An improved DSP has two internal data buses with two MAC units each receiving data from its respective data bus. A shifter is interposed between the multiply unit and the ALU and accumulate unit. The improved DSP also has a multiplexer interposed between one of the MAC units and the two data buses. The improved DSP is optimized to decode a received digital signal encoded in accordance with the Viterbi algorithm, wherein the DSP calculates a first pair of binary signals C. sub. 2n and C. sub. 2n+1 a Viterbi butterfly based upon a second pair of binary C. sub. n and C. sub. n+m/2, and a transitional signal a, in accordance with: C. sub. 2n =minimum (C. sub. n +a, C. sub. n+m/2 -a); C. sub. 2n+1 =minimum (C. sub. n -a, C. sub. n+m/2 +a).

Method And Apparatus To Determine The Frequency And Time Slot Position In A Digital Wireless Communication Session

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US Patent:
54917263, Feb 13, 1996
Filed:
Aug 17, 1993
Appl. No.:
8/107938
Inventors:
Nan-Sheng Lin - Union City CA
Mihran H. Touriguian - Hercules CA
Assignee:
TCSI Corp. - Berkeley CA
Sharp Corporation - Chiba
International Classification:
H03D 300
H04L 2722
US Classification:
375343
Abstract:
A digital wireless communication system operates between a first unit and a second unit. The received digitally encoded signal is sampled to produce a first sampled digital signal. A first bank of match filters with each match filter having a different frequency range is used to pass the first sampled digital signal therethrough. The output of the first bank of match filters having the largest amplitude is selected along with the match filter which produced the largest amplitude output. The digitally encoded signal having this "coarse" frequency range is then passed through a second bank of match filters. Each of the match filters has a fine frequency different from one another. The output of the second bank of match filters is produced and the output having the largest amplitude is selected. In addition, the filter producing the largest amplitude from the second bank of match filters is also selected.

Galois Field Polynomial Multiply/Divide Circuit And A Digital Signal Processor Incorporating Same

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US Patent:
56027672, Feb 11, 1997
Filed:
Aug 29, 1995
Appl. No.:
8/521112
Inventors:
Gerhard P. Fettweis - Dresden, DE
Mihran Touriguian - Hercules CA
Assignee:
TCSI Corporation - Berkeley CA
International Classification:
G06F 700
G06F 1500
US Classification:
3647461
Abstract:
The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.

Method And Apparatus For Adjusting The Sampling Phase Of A Digitally Encoded Signal In A Wireless Communication System

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US Patent:
54003687, Mar 21, 1995
Filed:
Aug 17, 1993
Appl. No.:
8/107451
Inventors:
Nan-Sheng Lin - Union City CA
Mihran Touriguian - Hercules CA
Kenkichi Suzuki - Ichikawa, JP
Assignee:
Teknekron Communications Systems, Inc. - Berkeley CA
International Classification:
H04L 700
US Classification:
375106
Abstract:
In a digital wireless communication system, a first unit transmits a digitally encoded signal to a second unit in a plurality of non-contiguous time slots. Within each time slot, the digitally encoded signal has a synchronization signal portion followed by a data signal portion. The second unit has an antenna to receive the synchronization signal portion of the digitally encoded signal. The second unit also has a clock to generate a clock signal at a first rate having a sampling phase. An analog to digital converter receives the clock signal and the synchronization signal and samples the synchronization signal at the first rate to generate a first plurality of symbols. An interpolator receives the first plurality of symbols and interpolates the first plurality of symbols to generate a second plurality of symbols at a second rate. The second rate is a multiple of the first rate. A match filter receives the second plurality of symbols and compares the second plurality symbol of symbols to a stored plurality of symbols to generate an error signal.

Digital Signal Processing Method And System Employing Separate Program And Data Memories To Store Data

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US Patent:
58322574, Nov 3, 1998
Filed:
Dec 29, 1995
Appl. No.:
8/581431
Inventors:
Mihran Touriguian - Hercules CA
Gerhard Fettweis - Dresden, DE
Ingrid Verbauwhede - Berkeley CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 900
US Classification:
395561
Abstract:
A digital signal processing system for executing instructions and processing data, including a program memory which stores the instructions and a first portion of the data, a data memory which stores a second portion of the data, and a program control unit connected to the program memory for receiving a sequence of the instructions and generating control signals for executing the instructions, wherein the program control unit is programmed to fetch at least one data value from the program memory in response to at least one of the instructions. Preferably, the system also includes a memory management unit connected to the program control unit and the data memory for generating address signals in response to at least one of the control signals for use in reading data values from the data memory. In preferred embodiments of the method of the invention, a digital signal processor (having a program memory which stores instructions and data and a physically separate data memory which stores data) generates control bits for controlling a read of data from the data memory in response to a first instruction from the program memory, and fetches data from the program memory in response to a second instruction from the program memory.

Method And System For Performing Arithmetic Operations With Single Or Double Precision

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US Patent:
57870250, Jul 28, 1998
Filed:
Feb 28, 1996
Appl. No.:
8/607937
Inventors:
Jumana A. Muwafi - San Francisco CA
Mihran Touriguian - Hercules CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 738
US Classification:
36473601
Abstract:
A circuit for performing either single precision or double precision arithmetic operations on data, a system including such a circuit, and a method implemented by the system. Preferably, the circuit is an arithmetic manipulation unit (AMU) which performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. The AMU concatenates two N-bit words in the double precision mode thus producing a 2N-bit operand, and performs a selected one of several arithmetic operations on the operand and a second 2N-bit operand. Preferably, the AMU performs a double precision operation in two cycles: a first cycle generating a first operand and loading the operand to an output register; and a second cycle in which a second operand is generated from a second pair of N-bit parts from the memory, the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands. The system preferably includes a multi-port memory, executes instructions in pipelined fashion, and operates in a single precision mode to fetch two N-bit operands from the memory in a single pipeline cycle using two address pointers and in a double precision mode to fetch two N-bit words from the memory in a single cycle. In a double precision mode, the system can fetch two N-bit parts stored in consecutive memory locations in a single cycle, by generating and asserting to the memory two addresses in response to one address pointer.

Method And Apparatus For Executing Nested Loops In A Digital Signal Processor

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US Patent:
57109133, Jan 20, 1998
Filed:
Dec 29, 1995
Appl. No.:
8/581167
Inventors:
Kumkum Gupta - Orinda CA
Mihran Touriguian - Hercules CA
Ingrid Verbauwhede - Berkeley CA
Harlan W. Neff - Castro Valley CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 932
US Classification:
395588
Abstract:
A digital signal processing system for executing instructions, including a program memory which stores the instructions and a program control unit for receiving and processing a sequence of the instructions to generate control signals for controlling operation of the system, and a loop circuit for use in such a program control unit. The loop circuit controls execution of a loop (preferably a nested loop) of a sequence of the instructions. Preferably, the loop circuit includes loop registers for storing loop start and end addresses and loop count values, and logic circuitry for implementing loops (including nested loops) in response to the addresses and count values in the loop registers. The loop circuit is initialized by loading appropriate addresses and values into the loop registers. After initialization, the loop circuit executes true zero overhead nested loops of instructions in the sense that the instructions to be looped need not include any initialization instructions, any special instruction to indicate the start of a loop or any dedicated branch instruction at the end of a loop for branching back to the start.
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Mihran H Touriguian from Hercules, CA, age ~60 Get Report