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Mihai Dan Budiu

from Sunnyvale, CA
Age ~53

Mihai Budiu Phones & Addresses

  • 955 Cambridge Ave, Sunnyvale, CA 94087
  • Pittsburgh, PA
  • Santa Clara, CA
  • Ithaca, NY

Publications

Us Patents

Repair-Policy Refinement In Distributed Systems

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US Patent:
8504874, Aug 6, 2013
Filed:
Sep 21, 2010
Appl. No.:
12/886566
Inventors:
Moises Goldszmidt - Palo Alto CA, US
Mihai Budiu - Sunnyvale CA, US
Yue Zhang - Sunnyvale CA, US
Michael Pechuk - Sammamish WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 11/00
US Classification:
714 25
Abstract:
In a distributed system a plurality of devices (including computing units, storage and communication units) are monitored by an automated repair service that uses sensors and performs one or more repair actions on computing devices that are found to fail according to repair policies. The repair actions include automated repair actions and non-automated repair actions. The health of the computing devices is recorded in the form of states along with the repair actions that were performed on the computing devices and the times at which the repair actions were performed, and events generated by both sensors and the devices themselves. After some period of the time, the history of states of each device, the events, and the repair actions performed on the computing devices are analyzed to determine the effectiveness of the repair actions. A statistical analysis is performed based on the cost of each repair action and the determined effectiveness of each repair action, and one or more of the policies may be adjusted, as well as determining from the signals and events from the sensors whether the sensors themselves require adjustment.

Optimizing Systems-On-A-Chip Using The Dynamic Critical Path

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US Patent:
20100180240, Jul 15, 2010
Filed:
Jan 13, 2009
Appl. No.:
12/353168
Inventors:
John D. Davis - San Francisco CA, US
Mihai Budiu - Sunnyvale CA, US
Hari Kannan - Stanford CA, US
International Classification:
G06F 17/50
US Classification:
716 5
Abstract:
The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

General Purpose Distributed Data Parallel Computing Using A High Level Language

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US Patent:
20100205588, Aug 12, 2010
Filed:
Feb 9, 2009
Appl. No.:
12/368231
Inventors:
Yuan Yu - Cupertino CA, US
Dennis Fetterly - Belmont CA, US
Michael Isard - San Francisco CA, US
Ulfar Erlingsson - Reykjavik, IS
Mihai Budiu - Sunnyvale CA, US
Assignee:
MICROSOFT CORPORATION - Redmond WA
International Classification:
G06F 9/45
G06F 15/16
US Classification:
717149, 709203, 717153
Abstract:
General-purpose distributed data-parallel computing using a high-level language is disclosed. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. The distributed execution plan is then executed on large compute clusters. Thus, the developer is allowed to write the program using familiar programming constructs in the high level language. Moreover, developers without experience with distributed compute systems are able to take advantage of such systems.

Visualizing Correlations In Multi-Dimensional Data

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US Patent:
20110199380, Aug 18, 2011
Filed:
Feb 15, 2010
Appl. No.:
12/705633
Inventors:
Mihai Budiu - Sunnyvale CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 11/20
G06F 3/048
US Classification:
345440, 715769, 715810
Abstract:
A system for visualizing correlations between attributes in a data set or across multiple data sets is provided. A user may view a graphical representation (e.g., a histogram) of attribute values for a first attribute. The user may assign a variety of graphical indicators to various value ranges of the first attribute. The user may view a graphical representation of the second attributes. The user may “drag and drop” the graphical representation of the first attributes onto the graphical representation of the second attributes. The graphical representation of the second attributes may be updated to incorporate the graphical elements assigned by the user to the value ranges of the first attribute. The user may visually see potential correlations between the first and the second attributes based on the graphical elements associated with the first attributes displayed with the associated second attributes.

Branch-And-Bound On Distributed Data-Parallel Execution Engines

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US Patent:
20120254597, Oct 4, 2012
Filed:
Mar 29, 2011
Appl. No.:
13/074006
Inventors:
Daniel Delling - Mountain View CA, US
Mihai Budiu - Sunnyvale CA, US
Renato F. Werneck - San Francisco CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/38
US Classification:
712233, 712E09045
Abstract:
A distributed data-parallel execution (DDPE) system splits a computational problem into a plurality of sub-problems using a branch-and-bound algorithm, designates a synchronous stop time for a “plurality of processors” (for example, a cluster) for each round of execution, processes the search tree by recursively using a branch-and-bound algorithm in multiple rounds (without inter-processor communications), determines if further processing is required based on the processing round state data, and terminates processing on the processors when processing is completed.

Modular Compilation Using Partial Compilers

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US Patent:
20130125099, May 16, 2013
Filed:
Nov 14, 2011
Appl. No.:
13/295107
Inventors:
Mihai Budiu - Sunnyvale CA, US
Gordon D. Plotkin - Edinburgh, GB
Joel Galenson - Berkeley CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/45
US Classification:
717140
Abstract:
A modular compiler architecture utilizes partial compiler modules that cooperatively produce object code for operation on a complex execution infrastructure. The partial compilers may invoke the services of other partial compilers, wherein each partial compiler operates as a self-contained “black-box” module. This structure, in turn, may allow the partial compilers of such implementations to be arranged in modular hierarchies for multi-level compilation and specialization of each partial compiler. These various implementations, in turn, produce compiled programs able to correctly run on large computer clusters comprising a mix of computational resources (machines, multiple cores, graphics cards, SQL server engines, etc.). Certain implementations may also be directed to compilers comprising modular partial compilers, and partial compilers may be formed from generalized forms of traditional compilers. Further disclosed is a set of high-level operations that manipulate partial compilers.

General Purpose Distributed Data Parallel Computing Using A High Level Language

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US Patent:
20170371721, Dec 28, 2017
Filed:
Jul 10, 2017
Appl. No.:
15/645620
Inventors:
- Redmond WA, US
Dennis Fetterly - Belmont CA, US
Michael Isard - San Francisco CA, US
Ulfar Erlingsson - Palo Alto CA, US
Mihai Budiu - Sunnyvale CA, US
Assignee:
Microsoft Technology Licensing, LLC - Redmond WA
International Classification:
G06F 9/52
G06F 9/45
G06F 9/44
Abstract:
General-purpose distributed data-parallel computing using a high-level language is disclosed. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. The distributed execution plan is then executed on large compute clusters. Thus, the developer is allowed to write the program using familiar programming constructs in the high level language. Moreover, developers without experience with distributed compute systems are able to take advantage of such systems.

Data-Plane Stateful Processing Units In Packet Processing Pipelines

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US Patent:
20170093987, Mar 30, 2017
Filed:
Sep 24, 2015
Appl. No.:
14/864088
Inventors:
- Palo Alto CA, US
Mihai Budiu - Sunnyvale CA, US
Changhoon Kim - Palo Alto CA, US
International Classification:
H04L 29/08
Abstract:
A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.
Mihai Dan Budiu from Sunnyvale, CA, age ~53 Get Report