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Michel R Frei

from Palo Alto, CA
Age ~63
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Also known as:
Michel Hong-Ha Frei, Michel Thihongha Frei, Michel V Frei, Machel R Frei
Phone and address:
236 Scripps Ct, Palo Alto, CA 94306
(510) 717-6072
Related to:
Daniel A Frei, 29Thi H Vuong, 63Alexandre Frei, 28
Connected to:
Adam L Frei, 53Amy L Frei, 50Ben A Frei, 92Brigitte Frei, 60Cheryl B Frei, 70David M Frei, 46Debra J Frei, 64Emily Frei, 38Florian Frei, 45Georg Frei, 63

Michel Frei Phones & Addresses

  • 236 Scripps Ct, Palo Alto, CA 94306 (510) 717-6072
  • Allentown, PA
  • 178 Rutgers Ave, Berkeley Heights, NJ 07922 (908) 464-4178 (908) 464-8579
  • Clinton, NJ
  • Red Bank, NJ
  • Annandale, NJ
  • Santa Clara, CA

Work

Company: Applied materials Feb 2006 Position: Engineer and director

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Princeton University 1990 Specialities: Electrical Engineering

Skills

C • Product Development

Languages

English

Industries

Semiconductors

Resumes

Resumes

Michel Frei Photo 1

Engineer And Director

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Location:
236 Scripps Ct, Palo Alto, CA 94306
Industry:
Semiconductors
Work:
Applied Materials
Engineer and Director
Lsi Corporation 2003 - 2005
Manager
Nokia Bell Labs 1992 - 2002
Distinguished Member of Technical Staff
Telcordia Technologies 1990 - 1992
Postdoc
Education:
Princeton University 1990
Doctorates, Doctor of Philosophy, Electrical Engineering Epfl (École Polytechnique Fédérale De Lausanne) 1978 - 1983
Skills:
C
Product Development
Languages:
English

Publications

Us Patents

Method And Apparatus For Modeling Electromagnetic Interactions In Electrical Circuit Metalizations To Simulate Their Electrical Characteristics

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US Patent:
6367053, Apr 2, 2002
Filed:
Apr 1, 1999
Appl. No.:
09/283395
Inventors:
Nathan R. Belk - Scotch Plains NJ
Michel Ranjit Frei - Berkeley Heights NJ
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
G06F 1750
US Classification:
716 2, 716 5, 716 12, 716 13, 716 14
Abstract:
Metalization structures are modeled by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections. Charge distributions are determined in those representative sub units based on the assumption that the integrated circuit substrate strongly suppresses any long range circuit interactions or frequency dependent effects.

Inductor Or Low Loss Interconnect And A Method Of Manufacturing An Inductor Or Low Loss Interconnect In An Integrated Circuit

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US Patent:
6395611, May 28, 2002
Filed:
Nov 1, 1999
Appl. No.:
09/432725
Inventors:
Nathan Belk - Scotch Plains NJ
William Thomas Cochran - Clermont FL
Michel Ranjit Frei - Berkeley Heights NJ
David Clayton Goldthorp - Reiffton PA
Shahriar Moinian - New Providence NJ
Kwok K. Ng - Warren NJ
Mark Richard Pinto - Summit NJ
Ya-Hong Xie - Beverly Hills CA
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H01L 2120
US Classification:
438381, 438383
Abstract:
An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Heterojunction Bipolar Transistor

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US Patent:
6509242, Jan 21, 2003
Filed:
Jan 12, 2001
Appl. No.:
09/759120
Inventors:
Michel Ranjit Frei - Berkeley Heights NJ
Clifford Alan King - New York NY
Yi Ma - Orlando FL
Marco Mastrapasqua - Annandale NJ
Kwok K Ng - Warren NJ
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 21331
US Classification:
438312, 438360, 257200, 257565, 257586
Abstract:
A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Solar Parametric Testing Module And Processes

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US Patent:
8049521, Nov 1, 2011
Filed:
Mar 24, 2009
Appl. No.:
12/409732
Inventors:
Danny Cam Toan Lu - San Francisco CA, US
Michel Marriott - Morgan Hill CA, US
Vicky Svidenko - Sunnyvale CA, US
Dapeng Wang - Santa Clara CA, US
Michel R. Frei - Palo Alto CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
G01R 27/08
H01L 31/042
US Classification:
324691, 136250
Abstract:
Embodiments of the present invention generally relate to a module that can test and analyze various regions of a solar cell device in an automated or manual fashion after one or more steps have been completed in the solar cell formation process. The module used to perform the automated testing and analysis processes can also be adapted to test a partially formed solar cell at various stages of the solar cell formation process within an automated solar cell production line. The automated solar cell production line is generally an arrangement of automated processing modules and automation equipment that is used to form solar cell devices.

Automated Integrated Solar Cell Production Line Composed Of A Plurality Of Automated Modules And Tools Including An Autoclave For Curing Solar Devices That Have Been Laminated

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US Patent:
8225496, Jul 24, 2012
Filed:
Aug 29, 2008
Appl. No.:
12/202199
Inventors:
Robert Z. Bachrach - Burlingame CA, US
Soo Young Choi - Fremont CA, US
Nicholas G. J. De Vries - Alameda CA, US
Yacov Elgar - Sunnyvale CA, US
Eric A. Englhardt - Palo Alto CA, US
Michel R. Frei - Palo Alto CA, US
Charles Gay - Westlake Village CA, US
Parris Hawkins - Los Altos CA, US
Choi (Gene) Ho - Sunnyvale CA, US
James Craig Hunter - Los Gatos CA, US
Penchala N. Kankanala - Santa Clara CA, US
Liwei Li - Sunnyvale CA, US
Danny Cam Toan Lu - San Francisco CA, US
Fang Mei - Foster City CA, US
Stephen P. Murphy - Perrysburg OH, US
Srujal (Steve) Patel - San Jose CA, US
Matthew J. B. Saunders - Sunnyvale CA, US
Asaf Schlezinger - Sunnyvale CA, US
Shuran Sheng - Sunnyvale CA, US
Tzay-Fa (Jeff) Su - San Jose CA, US
Jeffrey S. Sullivan - Castro Valley CA, US
David Tanner - San Jose CA, US
Teresa Trowbridge - Los Altos CA, US
Brice Walker - Bautista CA, US
John M. White - Hayward CA, US
Tae K. Won - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 51/44
H01L 51/48
H01L 21/768
H01L 31/072
US Classification:
29726, 29783, 29795, 29742, 29 33 P, 29890033
Abstract:
The present invention generally relates to a system that can be used to form a photovoltaic device, or solar cell, using processing modules that are adapted to perform one or more steps in the solar cell formation process. The automated solar cell fab is generally an arrangement of automated processing modules and automation equipment that is used to form solar cell devices. The automated solar fab will thus generally comprise a substrate receiving module that is adapted to receive a substrate, one or more absorbing layer deposition cluster tools having at least one processing chamber that is adapted to deposit a silicon-containing layer on a surface of the substrate, one or more back contact deposition chambers, one or more material removal chambers, a solar cell encapsulation device, an autoclave module, an automated junction box attaching module, and one or more quality assurance modules that are adapted to test and qualify the completely formed solar cell device.

Production Line Module For Forming Multiple Sized Photovoltaic Devices

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US Patent:
20090077804, Mar 26, 2009
Filed:
Aug 29, 2008
Appl. No.:
12/201840
Inventors:
Robert Z. Bachrach - Burlingame CA, US
Soo Young Choi - Fremont CA, US
Nicholas G.J. De Vries - Alameda CA, US
Yacov Elgar - Sunnyvale CA, US
Eric A. Englhardt - Palo Alto CA, US
Michel R. Frei - Palo Alto CA, US
Charles Gay - Westlake Village CA, US
Parris Hawkins - Los Altos CA, US
Choi (Gene) Ho - Sunnyvale CA, US
James Craig Hunter - Los Gatos CA, US
Penchala N. Kankanala - Santa Clara CA, US
Liwei Li - Sunnyvale CA, US
Danny Cam Toan Lu - San Francisco CA, US
Fang Mei - Foster City CA, US
Stephen P. Murphy - Perrysburg OH, US
Srujal (Steve) Patel - San Jose CA, US
Matthew J.B. Saunders - Sunnyvale CA, US
Asaf Schlezinger - Sunnyvale CA, US
Shuran Sheng - Sunnyvale CA, US
Tzay-Fa (Jeff) Su - San Jose CA, US
Jeffrey S. Sullivan - Castro Valley CA, US
David Tanner - San Jose CA, US
Teresa Trowbridge - Los Altos CA, US
Brice Walker - San Juan Bautista CA, US
John M. White - Hayward CA, US
Tae K. Won - San Jose CA, US
International Classification:
H01L 31/18
H01L 21/304
B26F 3/00
US Classification:
29890033, 225 1, 225 965, 225 97, 438462
Abstract:
The present invention generally relates to a sectioning module positioned within an automated solar cell device fabrication system. The solar cell device fabrication system is adapted to receive a single large substrate and form multiple silicon thin film solar cell devices from the single large substrate.

Process Testers And Testing Methodology For Thin-Film Photovoltaic Devices

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US Patent:
20090102502, Apr 23, 2009
Filed:
Oct 22, 2007
Appl. No.:
11/876346
Inventors:
Michel Ranjit Frei - Palo Alto CA, US
Tzay-Fa Su - San Jose CA, US
International Classification:
G01R 31/26
US Classification:
324765
Abstract:
The present invention generally relates to process testers and methods of fabricating the same using standard photovoltaic cell processes. In particular, the present invention relates to process tester layouts defined by laser scribing, methodology for creating process testers, methodology of using process testers for photovoltaic line diagnostics, placement of process testers in photovoltaic module production, and methodology for creating design rule testers.

Photovoltaic Fabrication Process Monitoring And Control Using Diagnostic Devices

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US Patent:
20090104342, Apr 23, 2009
Filed:
Sep 17, 2008
Appl. No.:
12/212594
Inventors:
Dapeng Wang - Santa Clara CA, US
Michel R. Frei - Palo Alto CA, US
Tzay-Fa (Jeff) Su - San Jose CA, US
Vicky Svidenko - San Jose CA, US
Gregg S. Higashi - San Jose CA, US
International Classification:
B05D 5/12
B05C 9/12
G01R 31/26
US Classification:
427 8, 427 74, 324765
Abstract:
The formation of diagnostic devices on the same substrate used to fabricate a photovoltaic (PV) cell is described. Such devices, also referred to as process diagnostic vehicles (PDVs), are configured for in-line monitoring of electrical characteristics of PV cell features and are formed on the substrate using the same process steps for PV cell fabrication. The data collected via the PDVs can be used to tune or optimize subsequent PV cell fabrication, i.e., used as feedback for the fabrication process. Alternatively, the data collected via PDVs can be fed forward in the fabrication process, so that later process steps performed on a PV cell substrate can be modified to compensate for issues detected on the PV cell substrate via the PDVs.
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Michel R Frei from Palo Alto, CA, age ~63 Get Report