Michael J Ziuchkovski

49821830, Jan 1, 1991

Jul 19, 1988

7/221747

Robert T. Flegal - Beaverton OR
Michael J. Ziuchkovski - Portland OR

Planar Systems, Inc. - Beaverton OR

G09G 330

340781

A matrix-addressed AC TFEL panel includes odd- and even-numbered scanning electrodes driven from opposite sides of the panel by separate power supplies. The data electrodes are divided into top and bottom sets so that they are arranged as complementary pairs extending towards each other slightly less than halfway across the screen leaving a small gap in the middle. The odd- and even-numbered scanning electrodes are divided into top and bottom subsets so that the top and bottom halves of the panel may be scanned simultaneously in line-by-line fashion. When an even electrode in the top half of the panel is scanned with a voltage of a first polarity, an odd electrode in the bottom half may be scanned with a voltage of an opposite polarity. Thus, the load for the scanning of the top and bottom halves is divided between positive and negative power supplies. To provide symmetric drive the polarities may be reversed each frame.

50103253, Apr 23, 1991

Dec 19, 1988

7/286231

Michael J. Ziuchkovski - Portland OR

Planar Systems, Inc. - Beaverton OR

G09G 330

340781

A driving network for a TFEL panel includes a frame capture buffer for flat panels having split-screen architecture to increase the video bandwidth and to allow for a high frame refresh rate without changing the video input rate. Input serial video data is converted to parallel data bits and latched at a predetermined clock rate. The latched data bits are transferred to appropriate buffer memories, one for each independently driven portion of the screen. Writing to the buffer memories and reading data out from the buffer memories occurs at asynchronous rates so that data in smaller bytes may be clocked in at a higher frequency and read out of the buffer memories in larger bytes at a lower frequency. Since data may be processed onto flat screen arrays in multiple bits per clock pulse, the frame repetition rate limitations inherent in processing serial input video data are avoided.

48933198, Jan 9, 1990

Dec 19, 1988

7/286288

Michael J. Ziuchkovski - Portland OR

Planar Systems, Inc. - Beaverton OR

H04L 704

375111

A clock regeneration circuit employing a digital phase locked loop for locking a video data signal to both a synchronization signal and a clock signal includes an oscillator for producing multiple phase clock signals, a synchronization latch circuit and a data latch circuit for selecting desired ones of the multiple phase clock signals, and a phase comparator for comparing the outputs of each of the latch circuits to produce an error signal which adjusts the phase of the synchronization signal to bring it into coincidence with the video data signal input. The phase adjusted synchronization signal controls the latching in the synchronization latch circuit and selects the appropriate phase of the multiple phase clock signals. In this way the horizontal synchronization pulses are locked to the video data and the locked horizontal synchronization pulses select a properly phased clock signal. In a matrix-addressed visual display, this ensures that the appropriate pixels are illuminated at the proper time.