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Michael F Starsinic

from Newtown, PA
Age ~49
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Also known as:
John F Starsinic, Michael E
Related to:
Patricia E Joma, 71Gerald J Starsinic, 77Damian M Starsinic, 27John J Keyburn, 72Gary J Dodson, 51April M Fulp, 46Jennifer M Keyburn, 47George J Starsinic, 14Karen C Dodson, 72Karen F Keyburn, 70Patricia Starsinic, 71Dorothy StarsinicAnne L Starsinic, 75Karen M Starsinic, 48
Connected to:
Edward R Starski, 41Janice Starsnic, 71Greg A Starstrom, 60Carol A Start, 87Donna F Start, 56Frank Start, 41James M Start, 74John E Start, 68Karen L Start, 83Sherwin A Start, 82

Michael Starsinic Phones & Addresses

  • Newtown, PA
  • 8712 Hickory Dr, Philadelphia, PA 19136 (215) 338-6557
  • 615 Hazell Ln, Philadelphia, PA 19116
  • Phila, PA

Work

Company: Motorola Mar 1998 to May 2000 Position: Engineer

Education

Degree: Master of Science, Masters School / High School: Villanova University 2000 to 2003 Specialities: Electrical Engineering

Skills

3Gpp • Lte • Wireless • Umts • Embedded Systems • Fpga • Embedded Software • System Architecture • Asic • Cellular Communications • Telecommunications • 4G • Mobile Technology • Debugging • M2M • Rtl Design • Iot • Patents • Innovation Management • Standards Development • Mobile Devices • Mobile Communications • Innovation • Femtocell

Industries

Wireless

Resumes

Resumes

Michael Starsinic Photo 1

Principal Engineer

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Location:
Philadelphia, PA
Industry:
Wireless
Work:
Motorola Mar 1998 - May 2000
Engineer
Interdigital Communications Mar 1998 - May 2000
Principal Engineer
Ametek Mar 1996 - Sep 1997
Intern
Education:
Villanova University 2000 - 2003
Master of Science, Masters, Electrical Engineering Drexel University 1994 - 1999
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
3Gpp
Lte
Wireless
Umts
Embedded Systems
Fpga
Embedded Software
System Architecture
Asic
Cellular Communications
Telecommunications
4G
Mobile Technology
Debugging
M2M
Rtl Design
Iot
Patents
Innovation Management
Standards Development
Mobile Devices
Mobile Communications
Innovation
Femtocell

Publications

Us Patents

Pipeline Architecture For Maximum A Posteriori (Map) Decoders

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US Patent:
6961921, Nov 1, 2005
Filed:
Jan 2, 2002
Appl. No.:
10/037609
Inventors:
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Philadelphia PA, US
Assignee:
Interdigital Technology Corporation - Wilmington DE
International Classification:
H03M013/03
US Classification:
716796, 714791
Abstract:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Pipeline Architecture For Maximum A Posteriori (Map) Decoders

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US Patent:
7181670, Feb 20, 2007
Filed:
Sep 6, 2005
Appl. No.:
11/219986
Inventors:
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Philadelphia PA, US
Assignee:
Interdigital Technology Corporation - Wilmington DE
International Classification:
H03M 13/00
H03M 13/03
US Classification:
714755, 714795, 714796, 375265, 375341
Abstract:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Software Parameterizable Control Blocks For Use In Physical Layer Processing

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US Patent:
7496074, Feb 24, 2009
Filed:
Apr 15, 2003
Appl. No.:
10/414125
Inventors:
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Philadelphia PA, US
David S. Bass - Great Neck NY, US
Binish Desai - Collegeville PA, US
Alan M. Levi - Swarthmore PA, US
George W. McClellan - Bensalem PA, US
Douglas R. Castor - Norristown PA, US
Assignee:
InterDigital Technology Corporation - Wilmington DE
International Classification:
H04B 7/216
US Classification:
370335, 370344, 370347
Abstract:
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Pipeline Architecture For Maximum A Posteriori (Map) Decoders

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US Patent:
7908545, Mar 15, 2011
Filed:
Jan 12, 2007
Appl. No.:
11/653014
Inventors:
Edward Hepler - Malvern PA, US
Michael F. Starsinic - Philadelphia PA, US
Assignee:
InterDigital Technology Corporation - Wilmington DE
International Classification:
H03M 13/03
US Classification:
714796, 714794, 714795, 375262, 375341
Abstract:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Software Parameterizable Control Blocks For Use In Physical Layer Processing

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US Patent:
8094653, Jan 10, 2012
Filed:
Feb 23, 2009
Appl. No.:
12/390719
Inventors:
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Newtown PA, US
David S. Bass - Great Neck NY, US
Binish P. Desai - San Diego CA, US
Alan M. Levi - Swarthmore PA, US
George W. McClellan - Bensalem PA, US
Douglas R. Castor - Norristown PA, US
Assignee:
InterDigital Technology Corporation - Wilmington DE
International Classification:
H04L 12/66
US Classification:
370381, 370463
Abstract:
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Umts Fdd Modem Optimized For High Data Rate Applications

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US Patent:
8295891, Oct 23, 2012
Filed:
Oct 20, 2008
Appl. No.:
12/254531
Inventors:
Douglas R. Castor - Norristown PA, US
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Newtown PA, US
William C. Hackett - Doylestown PA, US
David S. Bass - Great Neck NY, US
Joseph W. Gredone - Chalfont PA, US
Richard P. Gorman - Ivyland PA, US
Assignee:
Interdigital Technology Corporation - Wilmington DE
International Classification:
H04M 1/00
H01Q 11/12
US Classification:
455574, 4551271
Abstract:
A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.

Pipeline Architecture For Maximum A Posteriori (Map) Decoders

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US Patent:
8316285, Nov 20, 2012
Filed:
Mar 10, 2011
Appl. No.:
13/045041
Inventors:
Edward L. Hepler - Malvern PA, US
Michael F. Starsinic - Philadelphia PA, US
Assignee:
InterDigital Technology Corporation - Wilmington DE
International Classification:
H03M 13/00
US Classification:
714786, 714755, 375262, 375341
Abstract:
Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

Bandwidth Management For A Converged Gateway In A Hybrid Network

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US Patent:
8588793, Nov 19, 2013
Filed:
Dec 3, 2010
Appl. No.:
12/960128
Inventors:
John L. Tomici - Southold NY, US
John Cartmell - Lynbrook NY, US
Prabhakar R. Chitrapu - Blue Bell PA, US
Rocco Di Girolamo - Laval, CA
Jean-Louis Gauvreau - La Prairie, CA
Aravind Kamarajugadda - San Diego CA, US
Chunxuan Ye - Wayne PA, US
Alexander Reznik - Titusville NJ, US
Arty Chandra - Manhasset Hills NY, US
Kenneth F. Lynch - Wayne PA, US
Scott C. Hergenhan - Collegeville PA, US
Kushanava Laha - Gurgaon, IN
Reeteshkumar Varshney - Gurgaon, IN
Nicholas J. Podias - Brooklyn NY, US
Alpaslan Y. Demir - East Meadow NY, US
Martino Freda - Laval, CA
Dale N. Seed - Allentown PA, US
Michael F. Starsinic - Newtown PA, US
Athmane Touag - Laval, CA
Onkarnath Upadhyay - Maharajpur, IN
Paul L. Russell - Pennington NJ, US
Assignee:
InterDigital Patent Holdings, Inc. - Wilmington DE
International Classification:
H04W 40/00
H04B 1/38
H04W 72/00
H04W 4/00
H04M 1/00
US Classification:
455445, 455558, 455450, 4555521, 370331, 370338
Abstract:
Systems and methods for integrating bandwidth management (BWM) equipment into a network in order to manage the use of bandwidth over multiple radio access technologies (RATs) relating to communications between a wireless transmit receive unit and a mobile core network (MCN). When integrating itself into the network, a BWM server may be placed between a MCN and an femto access point. In order for WTRUs to communicate with the MCN through the femto access point and a BWM server, a BWM server may need deep packet inspection capabilities.
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Michael F Starsinic from Newtown, PA, age ~49 Get Report