Search

Michael Te Ni

from Palo Alto, CA
Age ~56
Get Report
Also known as:
Mike Ni, Michael Niu, Michael Nhotkeofa
Phone and address:
1840 Hamilton Ave, Palo Alto, CA 94303
Related to:
Maureen Y Birtcher, 70
Connected to:
Alice Ni, 30Angela C Ni, 45Ba Ni, 72Boo R Ni, 50Carolyn L Ni, 65Chi Ni, 104Chris Ni, 36Ella O Ni, 49Fanqi Ni, 35Hu Ni, 44

Michael Ni Phones & Addresses

  • 1840 Hamilton Ave, Palo Alto, CA 94303
  • 817 Bay Harbour Dr, Redwood City, CA 94065 (650) 598-9712
  • 64 Cove Ln, Redwood City, CA 94065 (650) 598-9712
  • Santa Monica, CA
  • 95 Cervantes Blvd, San Francisco, CA 94123 (415) 441-6912
  • Los Altos, CA
  • Redondo Beach, CA
  • Evanston, IL
  • Los Angeles, CA
  • Inverness, IL

Professional Records

Lawyers & Attorneys

Michael Ni Photo 1

Michael Ni - Lawyer

View page
ISLN:
1000601340
Admitted:
2008

Resumes

Resumes

Michael Ni Photo 2

Account Manager At Andrew Freeman & Co

View page
Location:
San Francisco Bay Area
Industry:
Public Relations and Communications
Michael Ni Photo 3

Experienced Product Executive, Entrepreneur, Provacateur

View page
Position:
CMO/SVP WW Marketing & Products at Avangate, Founder at VeraFirma
Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Work:
Avangate since 2011
CMO/SVP WW Marketing & Products
VeraFirma since Jun 2007
Founder
Amdocs 2010 - 2011
VP, Products
MyWire 2009 - 2010
GM/Managing Director - Global News Service
NetSuite Mar 2008 - Jun 2008
Interim Executive - Industry Solutions and Ecosystem Strategy
Education:
Harvard Business School Sep 1995 - Jun 1997
Stanford University 1990 - 1991
Massachusetts Institute of Technology 1986 - 1990
Skills:
Agent for Change
Entrepreneurship
SaaS
Enterprise Software
Cloud Computing
Marketing Strategy
Go-to-market Strategy
Product Marketing
Strategic Partnerships
E-commerce
Analytics
Business Alliances
Product Development
Mobile Devices
Product Management
Start-ups
Business Strategy
Innovation
Strategy
CRM
Business Development
Solution Selling
Sales Enablement
Online Marketing
Competitive Analysis
Business Intelligence
Michael Ni Photo 4

Chief Marketing Officer

View page
Location:
1840 Hamilton Ave, Palo Alto, CA 94303
Industry:
Computer Software
Work:
Financialforce
Chief Marketing Officer
Richrelevance
Board of Directors
Richrelevance
President and Cmo, Sales and Marketing
Richrelevance
Cmo, Strategy, Marketing, Ecosystem
Intapp 2016 - 2017
Svp, Product and Market Strategy
Education:
Harvard Business School Sep 1995 - Jun 1997
Master of Business Administration, Masters Stanford University 1990 - 1991
Master of Science, Masters, Engineering Massachusetts Institute of Technology 1986 - 1990
Bachelors, Bachelor of Science, Mechanical Engineering The American School
Harvard University
Master of Business Administration, Masters, Business
Skills:
Product Management
Enterprise Software
Strategy
Saas
Entrepreneurship
Cloud Computing
Crm
Start Ups
Strategic Partnerships
Go To Market Strategy
Business Strategy
E Commerce
Product Development
Product Marketing
Business Development
Leadership
Analytics
Competitive Analysis
Cross Functional Team Leadership
Business Intelligence
Sales
Mobile Devices
Marketing
Mobile Applications
Business Alliances
Professional Services
Software Industry
Marketing Strategy
Solution Selling
Lead Generation
Strategic Planning
It Strategy
P&L Management
B2B
Sales Enablement
Web Analytics
Demand Generation
Salesforce.com
Partner Management
Multi Channel Marketing
Online Marketing
Team Leadership
International Sales
Team Building
Sales Process
Global Business Development
Innovation
Mergers and Acquisitions
Channel Partners
Executive Management
Languages:
English
Mandarin
Michael Ni Photo 5

Michael Ni

View page
Michael Ni Photo 6

Right Track

View page
Work:

Right Track
Michael Ni Photo 7

Michael Ni

View page
Michael Ni Photo 8

Michael Ni

View page
Michael Ni Photo 9

Michael Ni

View page

Business Records

Name / Title
Company / Classification
Phones & Addresses
Michael Ni
President
N & J Silk Screen Printing Co
Lithographic Commercial Printing
2637 Durfee Ave, El Monte, CA 91732
3117 Adelia Ave, El Monte, CA 91733

Publications

Us Patents

Data Cache Virtual Hint Way Prediction, And Applications Thereof

View page
US Patent:
7594079, Sep 22, 2009
Filed:
Oct 11, 2006
Appl. No.:
11/545706
Inventors:
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
Vidya Rajagopalan - Palo Alto CA, US
Assignee:
MIPS Technologies, Inc. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711128, 711169
Abstract:
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Detection And Prevention Of Write-After-Write Hazards, And Applications Thereof

View page
US Patent:
20080082793, Apr 3, 2008
Filed:
Sep 29, 2006
Appl. No.:
11/529710
Inventors:
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
Assignee:
MIPS Technologies, Inc. - Mountain View CA
International Classification:
G06F 9/30
US Classification:
712218
Abstract:
Apparatuses, systems, and methods for detecting and preventing write-after-write hazards, and applications thereof. In an embodiment, a load/store queue of a processor stores a first register destination value associated with a graduated load instruction. A graduation unit of the processor broadcasts a second register destination value associated with a graduating load instruction. Control logic coupled to the load/store queue and the graduation unit compares the first register destination value to the second register destination. If the first register destination value and the second register destination value match, the control logic prevents the graduated load instruction from altering an architectural state of the processor.

Load/Store Unit For A Processor, And Applications Thereof

View page
US Patent:
20080082794, Apr 3, 2008
Filed:
Sep 29, 2006
Appl. No.:
11/529728
Inventors:
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
Assignee:
MIPS Technologies, Inc. - Mountain View CA
International Classification:
G06F 9/30
US Classification:
712218, 712225
Abstract:
A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Data Cache Virtual Hint Way Prediction, And Applications Thereof

View page
US Patent:
20100011166, Jan 14, 2010
Filed:
Sep 21, 2009
Appl. No.:
12/563840
Inventors:
Era K. NANGIA - Los Altos CA, US
Michael NI - Cupertino CA, US
Vidya RAJAGOPALAN - Palo Alto CA, US
Assignee:
MIPS Technologies, Inc. - Sunnyvale CA
International Classification:
G06F 12/08
G06F 12/00
US Classification:
711128, 711E12001, 711E12018
Abstract:
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Load/Store Unit For A Processor, And Applications Thereof

View page
US Patent:
20190220283, Jul 18, 2019
Filed:
Mar 27, 2019
Appl. No.:
16/366328
Inventors:
- Cambridge, GB
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
International Classification:
G06F 9/38
Abstract:
A load/store unit for a processor, and applications thereof In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to The particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Load/Store Unit For A Processor, And Applications Thereof

View page
US Patent:
20180203702, Jul 19, 2018
Filed:
Mar 12, 2018
Appl. No.:
15/918106
Inventors:
- Cambridge, GB
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
International Classification:
G06F 9/38
Abstract:
A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to The particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Data Cache Virtual Hint Way Prediction, And Applications Thereof

View page
US Patent:
20170192894, Jul 6, 2017
Filed:
Mar 23, 2017
Appl. No.:
15/467661
Inventors:
- Cambridge, GB
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
International Classification:
G06F 12/0862
G06F 12/0864
Abstract:
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Data Cache Virtual Hint Way Prediction, And Applications Thereof

View page
US Patent:
20150293853, Oct 15, 2015
Filed:
Jun 25, 2015
Appl. No.:
14/749932
Inventors:
- Cambridge, GB
Era K. Nangia - Los Altos CA, US
Michael Ni - Cupertino CA, US
Vidya Rajagopalan - Palo Alto CA, US
International Classification:
G06F 12/08
Abstract:
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.
Control profile
Michael Te Ni from Palo Alto, CA, age ~56 Get Report