Resumes
Resumes
Michael Cotsford Phones & Addresses
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Medway, MA
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7 Jenpaul Way, Milford, MA 01757 (508) 381-0223
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7B Jenpaul Way, Milford, MA 01757
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62 Mellen St, Bellingham, MA 02019 (508) 560-7910
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557 Worcester Rd, Framingham, MA 01701 (508) 875-0436
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27 Briarwood Ln, Marlborough, MA 01752 (508) 303-6757
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Lexington, SC
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62 Mellen St, Bellingham, MA 02019
Work
Position:
Food Preparation and Serving Related Occupations
Education
Degree:
High school graduate or higher
Publications
Us Patents
Multi-Threaded Pipeline With Context Issue Rules
View pageUS Patent:
20040034759, Feb 19, 2004
Filed:
Oct 17, 2002
Appl. No.:
10/274427
Inventors:
Solomon Katzman - Santa Cruz CA, US
Michael Cotsford - Milford MA, US
Robert Gelinas - Needham MA, US
W. Hays - Cambridge MA, US
Todd Snyder - Waltham MA, US
Michael Cotsford - Milford MA, US
Robert Gelinas - Needham MA, US
W. Hays - Cambridge MA, US
Todd Snyder - Waltham MA, US
Assignee:
Lexra, Inc. - Waltham MA
International Classification:
G06F009/00
G06F015/76
G06F015/00
G06F015/76
G06F015/00
US Classification:
712/001000
Abstract:
An apparatus and method for increasing throughput in a processor having a multi-threaded pipeline is provided. Throughput is increased by dynamically allocating hardware contexts to pipeline flows according to context issue rules. The context issue rules eliminate some hardware bypass paths allowing for a shorter clock period and minimize pipeline stalls. One context issue rule eliminates the need for an E-E bypass path by ensuring that no context is allowed to issue in two adjacent pipeline flows. Another context issue rule eliminates the need for an M-E bypass path by ensuring that data retrieved from memory in a pipeline flow for a context is available prior to a successive pipeline flow for the same context entering the execution stage. A beat issue rule looks for reduced utilization of the pipeline when no active context can issue an instruction due to the context issue rules. By application of the context issue rules, a multi-threaded pipeline can be kept filled and operating at 100% efficiency with as little as two concurrent contexts issuing in alternating cycles.
Peripheral Component Interconnect Attributes Shared Using Address Bits
View pageUS Patent:
20220350756, Nov 3, 2022
Filed:
May 3, 2021
Appl. No.:
17/306033
Inventors:
- Yokneam, IL
Ilan Pardo - Ramat-Hasharon, IL
Yamin Friedman - Haifa, IL
Michael Cotsford - Bellingham MA, US
Mark Rosenbluth - Uxbridge MA, US
Hillel Chapman - Ramat Hashofet, IL
Ilan Pardo - Ramat-Hasharon, IL
Yamin Friedman - Haifa, IL
Michael Cotsford - Bellingham MA, US
Mark Rosenbluth - Uxbridge MA, US
Hillel Chapman - Ramat Hashofet, IL
International Classification:
G06F 13/16
G06F 13/42
G06F 13/38
G06F 12/02
G06F 12/0811
G06F 15/78
G06F 13/42
G06F 13/38
G06F 12/02
G06F 12/0811
G06F 15/78
Abstract:
A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.