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Michael David Cesky

from Raleigh, NC
Age ~41
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Also known as:
Michael D Cesky, Michael B Cesky
Phone and address:
11715 Shavenrock Pl, Raleigh, NC 27613
Related to:
Michael Molyneux, 80Jennifer L O'Halloran, 33Sharon Cesky, 42Marivel Huertas, 65Veronica M Huertas, 35Eduardo M Huertas, 66Nikki HuertasManuel HuertasSharon Huertas, 42David C Cesky, 71Thomas C O'Halloran, 45
Connected to:
Jennifer E Ceslak, 60Jesse D Cesmat, 41Michael W Cesmat, 57Adam C Cesnales, 52Amanda J Cesnick, 35Carlos E Cesnik, 61Carol A Cesnik, 59Amaury Cespedes, 52Andres Cespedes, 86Antonio Cespedes, 45

Michael Cesky Phones & Addresses

  • 11715 Shavenrock Pl, Raleigh, NC 27613
  • Mebane, NC
  • 4473 Baraboo St, Rochester, MN 55901
  • 3625 41St St, Rochester, MN 55901
  • 310 Hall St, Bel Air, MD 21014 (410) 776-3239
  • Princeville, HI

Resumes

Resumes

Michael Cesky Photo 1

Senior Physical Design Engineer

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Location:
11715 Shavenrock Pl, Raleigh, NC 27613
Industry:
Information Technology And Services
Work:
Qualcomm
Senior Physical Design Engineer
Ibm Feb 2005 - Dec 2014
Physical Design and Integration Engineering Professional
Education:
University of Delaware 2001 - 2005
Bachelor of Engineering, Bachelors, Electrical Engineering
Skills:
Placement Driven Synthesis
Cadence Space Based Router and Chip Optimizer
Static Timing Analysis
Power Grid Planning and Generation
Floorplanning
Physcial Verification
Noise Analysis and Improvement
Cadence Encounter
Pattern Generators and Oscilloscopes
45 Nm Ibm Technologies
Physical Design
Integration
Cadence
Michael Cesky Photo 2

Senior Physical Design Engineer

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Location:
Raleigh, NC
Work:
Microsoft
Senior Physical Design Engineer
Education:
University of Delaware 2001 - 2005
Bachelor of Engineering, Bachelors

Publications

Us Patents

Method And Enhanced Phase Locked Loop Circuits For Implementing Effective Testing

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US Patent:
7538625, May 26, 2009
Filed:
Feb 27, 2007
Appl. No.:
11/679323
Inventors:
Michael David Cesky - Rochester MN, US
James David Strom - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03L 7/00
H03L 7/06
US Classification:
331 51, 331 18, 331 25, 331 16, 327156, 327157
Abstract:
A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.

Auto-Routing Small Jog Eliminator

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US Patent:
7707522, Apr 27, 2010
Filed:
Nov 14, 2007
Appl. No.:
11/939761
Inventors:
Mark R. Beckenbaugh - Rochester MN, US
Michael D. Cesky - Rochester MN, US
Jay A. Lawrence - Rochester MN, US
Lily L. Wang - Rochester MN, US
Nicholas G. Young - Rochester MN, US
John W. Zack - Rochester MN, US
Laura M. Zumbrunnen - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 1, 716 13, 716 19
Abstract:
In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.

Method And Enhanced Phase Locked Loop Circuits For Implementing Effective Testing

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US Patent:
20080208541, Aug 28, 2008
Filed:
Oct 10, 2007
Appl. No.:
11/870159
Inventors:
Michael David Cesky - Rochester MN, US
James David Strom - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
703 1
Abstract:
A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.

Derived Level Recognition In A Layout Editor

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US Patent:
20090077518, Mar 19, 2009
Filed:
Sep 18, 2007
Appl. No.:
11/856819
Inventors:
Mark R. Beckenbaugh - Rochester MN, US
Michael D. Cesky - Rochester MN, US
Jay A. Lawrence - Rochester MN, US
Lily L. Wang - Rochester MN, US
Nicholas G. Young - Rochester MN, US
John W. Zack - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 11
Abstract:
A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a plurality of layers within a design, identifying at least one of a derived level and a device defined within the plurality; and displaying the at least one derived level and device to a user.

System And Method For Auto-Routing Jog Elimination

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US Patent:
7530042, May 5, 2009
Filed:
May 20, 2008
Appl. No.:
12/124120
Inventors:
Mark R. Beckenbaugh - Rochester MN, US
Michael D. Cesky - Rochester MN, US
Nicholas G. Young - Rochester MN, US
John W. Zack - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 13, 716 12, 716 14
Abstract:
A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and dividing the first width difference by the width of the source; detecting a second size differential between the wire and the source if the first size differential is less than a maximum length percentage by calculating a second width difference between the width of the source and a width of the wire, and dividing the second width difference by the width of the source; and modifying a size of the wire if the second size differential is less than a maximum width percentage.

System And Method For Auto-Routing Jog Elimination

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US Patent:
7530041, May 5, 2009
Filed:
May 20, 2008
Appl. No.:
12/124119
Inventors:
Mark R. Beckenbaugh - Rochester MN, US
Michael D. Cesky - Rochester MN, US
Nicholas G. Young - Rochester MN, US
John W. Zack - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 13, 716 12, 716 14
Abstract:
A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividing the width difference by the width of the wire; and modifying a size of the wire if the first size differential is less than a maximum width percentage and if a length of the source is less than a length range specified by a user.
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Michael David Cesky from Raleigh, NC, age ~41 Get Report