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Michael J Budwey

from Holliston, MA
Age ~71
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Also known as:
Michael Jacob Budwey, Michael R Budwey, Michael J Budway, Michael J Haggerty, Mike Budwey
Phone and address:
149 Rolling Meadow Dr, Holliston, MA 01746
(508) 429-9802
Connected to:
Kirsten M Budwey, 62Stephanie A Budwey, 44Jordan Budwick, 34Andrew Budwig, 70Melissa C Budwig, 43Ralph S Budwig, 69Leeronald Budwine, 42Randi B Budwit, 72Jack M Budwitz, 109Marie K Budworth, 103

Michael Budwey Phones & Addresses

  • 149 Rolling Meadow Dr, Holliston, MA 01746 (508) 429-9802
  • 49 Rolling Meadow Dr, Holliston, MA 01746 (508) 429-9802
  • Cambridge, MA
  • Malden, MA
  • Somerville, MA

Industries

Computer Hardware

Resumes

Resumes

Michael Budwey Photo 1

Michael Budwey

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Location:
Greater Boston Area
Industry:
Computer Hardware

Publications

Us Patents

Systems And Methods For Checkpointing

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US Patent:
7496787, Feb 24, 2009
Filed:
Apr 29, 2005
Appl. No.:
11/118869
Inventors:
John Edwards - Clinton MA, US
Michael Budwey - Holliston MA, US
Assignee:
Stratus Technologies Bermuda Ltd. - Hamilton
International Classification:
G06F 11/00
US Classification:
714 13, 714 15
Abstract:
The invention relates to checkpointing memory. In one aspect, a processor directs a write request to a location within a first memory. The write request includes at least a data payload and an address identifying the location. An inspection module identifies the write request before it reaches the first memory, copies at least the address identifying the location, and forwards the write request to a memory agent within the first memory.

Memory Back Up System With One Cache Memory And Two Physically Separated Main Memories

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US Patent:
48191540, Apr 4, 1989
Filed:
Dec 4, 1986
Appl. No.:
6/937978
Inventors:
Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA
Assignee:
Sequoia Systems, Inc. - Marlborough MA
International Classification:
G06Z 1116
US Classification:
364200
Abstract:
Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks.

Self-Checking Computer Circuitry

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US Patent:
45410941, Sep 10, 1985
Filed:
Mar 21, 1983
Appl. No.:
6/477536
Inventors:
Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA
Assignee:
Sequoia Systems, Inc. - Marlboro MA
International Classification:
G06F 1116
US Classification:
371 68
Abstract:
Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults. In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half. To provide error detection, address information and data sent from each control unit to its associated memory is compared between circuit halves.

Memory Back-Up System

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US Patent:
46548190, Mar 31, 1987
Filed:
Jun 28, 1985
Appl. No.:
6/750652
Inventors:
Jack J. Stiffler - Concord MA
Michael J. Budwey - Holliston MA
James M. Nolan - Holliston MA
Assignee:
Sequoia Systems, Inc. - Marlborough MA
International Classification:
G06F 1116
US Classification:
364900
Abstract:
Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks.

Modular Computer System

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US Patent:
44842732, Nov 20, 1984
Filed:
Sep 3, 1982
Appl. No.:
6/414961
Inventors:
Jack J. Stiffler - Concord MA
Richard A. Karp - Bedford MA
James M. Nolan - Holliston MA
Michael J. Budwey - Holliston MA
David A. Wallace - Chelmsford MA
Assignee:
Sequoia Systems, Inc. - Marlborough MA
International Classification:
G06F 1516
US Classification:
364200
Abstract:
A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.

Modular Computer System

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US Patent:
46086315, Aug 26, 1986
Filed:
Nov 19, 1984
Appl. No.:
6/672799
Inventors:
Jack J. Stiffler - Concord MA
Richard A. Karp - Bedford MA
James M. Nolan - Holliston MA
Michael J. Budwey - Holliston MA
David A. Wallace - Chelmsford MA
Assignee:
Sequoia Systems, Inc. - Marlborough MA
International Classification:
G06F 1516
US Classification:
364200
Abstract:
A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.
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Michael J Budwey from Holliston, MA, age ~71 Get Report