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Michael D Barrell

from Longmont, CO
Age ~46
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Also known as:
Michael David Barrell, Michael David Barrel, Mike Barrell, Michael Barnell
Connected to:
Ashlee P Barrella, 45Catherine A Barrell, 44Chad J Barrelli, 48Christine M Barrella, 36Doris S Barrell, 68Ila G Barrell, 63Jessica B Barrell, 42Joyce A Barrell, 80Nathan Barrell, 39Perry R Barrell, 83

Michael Barrell Phones & Addresses

  • Longmont, CO
  • Superior, CO
  • 4940 Meredith Way, Boulder, CO 80303 (303) 449-3230
  • Worcester, MA
  • Albany, NY
  • Superior, CO
  • Troy, NY
  • 4940 Meredith Way APT 103, Boulder, CO 80303 (303) 887-6709

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Michael Barrell Photo 1

Managing Principal Engineer

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Location:
Longmont, CO
Industry:
Computer Hardware
Work:
Seagate Technology
Managing Principal Engineer
Seagate Technology
Principal Software Engineer
Dot Hill Systems Aug 2014 - Oct 2015
Software Architect
Dot Hill Systems Jul 2012 - Aug 2014
Principal Software Engineer
Dot Hill Systems Mar 2008 - Jul 2012
Senior Software Engineer
Education:
Rensselaer Polytechnic Institute 1996 - 2000
Bachelors, Electrical Engineering, Computer Systems Engineering
Skills:
Firmware
Storage
Scsi
Raid
Debugging
Device Drivers
Embedded Systems
Fibre Channel
Perl
Iscsi
Kernel
Embedded Software
C
Sata
System Architecture
Ssd
San
Python
Arm
Rtos
X86
Software Engineering
File Systems
Logic Analyzer
C++
Michael Barrell Photo 2

Michael Barrell

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Michael Barrell Photo 3

Michael Barrell

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Location:
Greater Denver Area
Industry:
Computer Hardware
Skills:
SCSI
Firmware
iSCSI
SATA
Kernel
Storage
Fibre Channel
RAID
SAN
Embedded Systems
Embedded Software
RTOS
X86
Device Drivers
Software Engineering
File Systems
Perl
Logic Analyzer
C
Debugging
Python

Business Records

Name / Title
Company / Classification
Phones & Addresses
Michael Barrell
President
NA ATSESTA RESOURCES, INC

Publications

Us Patents

Tape Cartridge Format Identification In A Single Reel Tape Handling Device

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US Patent:
20030173438, Sep 18, 2003
Filed:
Feb 4, 2003
Appl. No.:
10/357870
Inventors:
Stephen Stamm - Fort Lupton CO, US
James Kuhar - Broomfield CO, US
Michael Barrell - Boulder CO, US
International Classification:
G11B023/107
US Classification:
242/348000
Abstract:
Methods and apparatuses for identifying a single reel tape cartridge format, in a single reel tape handling device, from a plurality of available formats. According to one aspect of the invention, cartridge identification information is provisioned on a single reel tape cartridge leader. The cartridge identification information is detectable by the tape handling device and usable to identify a format of the tape cartridge from a plurality of available formats. The cartridge identification information includes at least one feature on the tape cartridge leader having characteristics indicative to the tape handling device of the format of the tape cartridge presented to the tape handling device.

Write Cache Management Method And Apparatus

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US Patent:
20130326149, Dec 5, 2013
Filed:
May 29, 2012
Appl. No.:
13/482314
Inventors:
Michael David Barrell - Superior CO, US
Zachary David Traut - Denver CO, US
Assignee:
DOT HILL SYSTEMS CORPORATION - Longmont CO
International Classification:
G06F 12/08
US Classification:
711135
Abstract:
A method for destaging data from a memory of a storage controller to a striped volume is provided. The method includes determining if a stripe should be destaged from a write cache of the storage controller to the striped volume, destaging a partial stripe if a full stripe write percentage is less than a full stripe write affinity value, and destaging a full stripe if the full stripe write percentage is greater than the full stripe write affinity value. The full stripe write percentage includes a full stripe count divided by the sum of the full stripe count and a partial stripe count. The full stripe count is the number of stripes in the write cache where all chunks of a stripe are dirty. The partial stripe count is the number of stripes where at least one chunk but less than all chunks of the stripe are dirty.

Preserving Data Integrity During Controller Failures

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US Patent:
20220261322, Aug 18, 2022
Filed:
May 4, 2022
Appl. No.:
17/736351
Inventors:
- Fremont CA, US
Ritvik Viswanatha - Longmont CO, US
Michael Barrell - Longmont CO, US
International Classification:
G06F 11/20
G06F 12/0806
Abstract:
Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.

Write And Compare Only Data Storage

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US Patent:
20210240363, Aug 5, 2021
Filed:
Jan 30, 2020
Appl. No.:
16/777722
Inventors:
- Cupertino CA, US
Jess LACY - Longmont CO, US
Michael BARRELL - Longmont CO, US
International Classification:
G06F 3/06
G06F 21/62
H04L 29/06
Abstract:
The presently disclosed technology is directed to combatting data theft, particularly of verified authentication data (or hashes thereof) such as login information, thumbprint data, digital signatures, identification numbers, and any other data that should be known to an accessor of stored data. The verified authentication data is initially saved for later comparison in a new type of memory, write-and-compare-only memory, where the data may be queried as to whether a to-be-verified value matches the stored verified value, but the stored and verified data is not read from the write-and-compare-only memory. This prevents a data breach by preventing the verified authentication data from being read by anyone, including those with access (whether legitimate or illegitimate) to any system connected to the write-and-compare-only memory.

Data Storage System With Write Back Cache

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US Patent:
20200089609, Mar 19, 2020
Filed:
Sep 19, 2018
Appl. No.:
16/135576
Inventors:
- Cupertino CA, US
Michael Barrell - Longmont CO, US
Richard O. Weiss - Superior CO, US
Mohamad H. El-Batal - Superior CO, US
International Classification:
G06F 12/0804
G06F 13/16
G06F 13/42
Abstract:
A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.

Network Data Storage Buffer System

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US Patent:
20180335961, Nov 22, 2018
Filed:
May 17, 2017
Appl. No.:
15/597881
Inventors:
- Cupertino CA, US
Michael Barrell - Longmont CO, US
International Classification:
G06F 3/06
G06F 13/42
Abstract:
A data storage network may have multiple data storage devices that each consist of a device buffer. A network buffer and buffer circuit can be found in a network controller with the buffer circuit arranged to divide and store data associated with a data access request in the network buffer and the device buffer of the first data storage device.

Read Ahead Management In A Multi-Stream Workload

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US Patent:
20180067860, Mar 8, 2018
Filed:
Sep 8, 2016
Appl. No.:
15/259998
Inventors:
- Cupertino CA, US
Michael D. Barrell - Superior CO, US
International Classification:
G06F 12/0862
Abstract:
Implementations described and claimed herein provide a method and system for managing execution of commands for a storage device, the method comprising identifying individual streams processing read ahead operations in a storage controller, determining an amount of read ahead data that each individual stream is processing in the read ahead operations, determining a total amount of read cache available for the storage controller, and determining a total amount of read ahead data that all the individual streams are processing in the read ahead operations.

Method And Apparatus For Processing Slow Infrequent Streams

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US Patent:
20150169450, Jun 18, 2015
Filed:
Feb 23, 2015
Appl. No.:
14/628882
Inventors:
- Longmont CO, US
Michael David Barrell - Superior CO, US
Assignee:
DOT HILL SYSTEMS CORPORATION - Longmont CO
International Classification:
G06F 12/08
Abstract:
A method for efficiently processing write data from a storage controller to a striped storage volume is provided. The method includes receiving, by the storage controller, a host write request including a host write request size, calculating, by the storage controller, that a time to fill a stripe including the host write request is not less than a host guaranteed write time, and processing, by the storage controller, the host write request as a write-through host write request. The time to fill the stripe is a size of the stripe divided by a data rate of a host write stream comprising the host write request. The host guaranteed write time is the maximum latency that the storage controller guarantees host write requests are committed to one of a storage controller write cache and the striped storage volume.
Control profile
Michael D Barrell from Longmont, CO, age ~46 Get Report