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Micah Tr Barany

from Portland, OR
Age ~59
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Related to:
Preston D Hicks, 57Moe R KirschenbaumNoah LumbantobingYael Barany, 27Noah Lumbantobing, 29Rebecca Lumbantobing, 26
Connected to:
Agnes Baranyai, 39Gabor Baranyai, 42George Baranyai, 59Jeffrey Barany, 55Kirsty Barany, 46Anita Baranyi, 44Marisela Baranyk, 33Mario Baranzini, 35Richard D Baranzini, 78Tracy N Baranzyk, 45

Micah Barany Phones & Addresses

  • 2015 Kanan St, Portland, OR 97201 (503) 827-5668 (503) 977-0575
  • 3140 Cascade Ave, Portland, OR 97201 (503) 827-5668
  • Palo Alto, CA

Work

Company: Intel corporation Oct 1989 Position: Engineer

Education

Degree: Master of Science, Masters School / High School: Stanford University 1992 to 1993 Specialities: Electronics Engineering

Skills

Semiconductors • Microprocessors • Hardware Architecture • Intel • Power Management • Processors • Computer Architecture • Rtl Design • Soc • Vlsi • Debugging • Verilog

Industries

Computer Hardware

Resumes

Resumes

Micah Barany Photo 1

Engineer

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Location:
Portland, OR
Industry:
Computer Hardware
Work:
Intel Corporation
Engineer
Education:
Stanford University 1992 - 1993
Master of Science, Masters, Electronics Engineering Uc San Diego 1983 - 1989
Bachelors, Bachelor of Science, Physics, Engineering
Skills:
Semiconductors
Microprocessors
Hardware Architecture
Intel
Power Management
Processors
Computer Architecture
Rtl Design
Soc
Vlsi
Debugging
Verilog

Publications

Us Patents

Low Power Operation Mechanism And Method

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US Patent:
6650171, Nov 18, 2003
Filed:
Oct 15, 2002
Appl. No.:
10/270198
Inventors:
Kevin X. Zhang - Portland OR
Micah Barany - Portland OR
Krishnan Ravichandran - Saratoga CA
Bob Jackson - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 301
US Classification:
327534
Abstract:
An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.

Low Power Operation Mechanism And Method

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US Patent:
6483375, Nov 19, 2002
Filed:
Jun 28, 2001
Appl. No.:
09/892632
Inventors:
Kevin X. Zhang - Portland OR
Micah Barany - Portland OR
Krishnan Ravichandran - Saratoga CA
Bob Jackson - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 301
US Classification:
327534
Abstract:
An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.

Processor Power Monitoring And Control With Dynamic Load Balancing

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US Patent:
20170285710, Oct 5, 2017
Filed:
Apr 1, 2016
Appl. No.:
15/088531
Inventors:
- Santa Clara CA, US
Ian M. Steiner - Hillsboro OR, US
Jonathan M. Eastep - Portland OR, US
Richard J. Greco - West Linn OR, US
Krishnakanth V. Sistla - Beaverton OR, US
Micah Barany - Portland OR, US
Andrew J. Herdrich - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/28
Abstract:
Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.
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Micah Tr Barany from Portland, OR, age ~59 Get Report