Merwin H Alferness

6629236, Sep 30, 2003

Nov 12, 1999

09/439581

Anthony Gus Aipperspach - Rochester MN
Merwin Herscher Alferness - Rochester MN
Gregory John Uhlmann - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 938

712228, 709108, 327203

A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in a scan mode for testing purposes. In scan mode, one or more elements which normally function as master elements, function as slave elements. When operating in scan mode using this arrangement, the number of master elements in the pair of cells equals the number of slave elements, even though the number of master elements exceeds the number of slave elements during normal operation, permitting data to be successively scanned through all elements of the circuit. In an alternative embodiment, elements function as in scan mode during a HOLD mode of operation, and a feedback loop controlled by a HOLD signal is added to each pair of master/slave elements. The feedback loop drives the master element with the value of the slave.

7069557, Jun 27, 2006

May 23, 2002

10/153995

Merwin Herscher Alferness - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 9/46

718102, 709230, 709236, 370230, 370233, 370235, 3703952, 37039572, 370397, 370413, 712 6, 712 16

A virtual path feature in which several virtual channels share an assigned amount of bandwidth is implemented in a network processor. The network processor maintains a schedule indicative of respective times at which a plurality of virtual channels are to be serviced. An entry is read from the schedule. The entry corresponds to a current transmit cycle and includes a pointer to a channel descriptor for a virtual channel to be serviced in the current transmit cycle. A data cell for the virtual channel to be serviced in the current cycle is transmitted. An entry is added to the schedule to point to a channel descriptor that is pointed to by the channel descriptor for the virtual channel serviced in the current transmit cycle.

7130270, Oct 31, 2006

Jul 26, 2002

10/206170

Merwin Herscher Alferness - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

International Business Machines Corporation - Armonk NY

H04J 1/16

370235, 370399

In a scheduler circuit for a network processor, bandwidth assigned to a virtual path is allocated among virtual channels associated with the virtual path. The allocation of bandwidth among the virtual channels is varied dynamically as virtual channels become active or inactive.

20030200424, Oct 23, 2003

Jun 10, 2003

10/459646

Anthony Aipperspach - Rochester MN, US
Merwin Alferness - Rochester MN, US
Gregory Uhlmann - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F009/44

712/228000

A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in multiple modes, including a scan mode for testing purposes.

20050066144, Mar 24, 2005

Sep 18, 2003

10/667029

Merwin Alferness - Rochester MN, US
William Goetzinger - Rochester MN, US
Kent Haselhorst - Byron MN, US
Lonny Lambrecht - Byron MN, US
Joshua Rensch - Rochester MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F012/00

711170000

In a first aspect, a first method is provided for self-adjusting allocation of memory bandwidth in a network processor system. The first method includes the steps of (1) determining an amount of memory bandwidth of a network processor used by each of a plurality of data types; and (2) dynamically adjusting the amount of memory bandwidth allocated to at least one of the plurality of data types based on the determination. Numerous other aspects are provided.

62789597, Aug 21, 2001

Mar 19, 1999

9/273184

Merwin Herscher Alferness - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 1500

702186

A data processing system and method of monitoring the performance of a data processing system in processing data requests, where said data processing system processes data requests within a multilevel memory hierarchy. At least one token is passed with a data request along a particular path within the multilevel memory hierarchy. The time duration for the token to completely pass along the particular path is stored if expected conditions are encountered along the particular path within the multilevel memory hierarchy, such that the performance of said data processing system requesting data along that particular path under the expected conditions is determined and is available for subsequent performance monitoring.