Melvin W Stene

7342985, Mar 11, 2008

Jun 24, 2003

10/602195

Melvin W. Stene - Pocatello ID, US

AMI Semiconductor, Inc. - Pocatello ID

H03D 3/24

375376, 375373, 327149, 327158

Digital delay locked loops which generate fixed angle delayed (e. g. , quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature delay elements is calculated based on the number of delay elements needed to provide one or more cycles of delay, and adjusted to reflect system clock delay. The digital delay locked loop also acquires a locked state quickly by sampling more frequently before acquiring the lock than after. Furthermore, jitter is reduced by introducing hysteresis into the sampling process, and by disabling the delay element adjustment process during jitter sensitive times. Lock stability is improved by introducing hysteresis into the lock detection process.

7526056, Apr 28, 2009

Oct 30, 2007

11/929765

Melvin W. Stene - Pocatello ID, US

Semiconductor Components Industries, LLC - Phoenix AZ

H03D 3/24

375376, 375373, 327149, 327158

Digital delay locked loops which generate fixed angle delayed (e. g. , quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature delay elements is calculated based on the number of delay elements needed to provide one or more cycles of delay, and adjusted to reflect system clock delay. The digital delay locked loop also acquires a locked state quickly by sampling more frequently before acquiring the lock than after. Furthermore, jitter is reduced by introducing hysteresis into the sampling process, and by disabling the delay element adjustment process during jitter sensitive times. Lock stability is improved by introducing hysteresis into the lock detection process.

20020109495, Aug 15, 2002

Dec 19, 2000

09/741317

James Antone - Austin TX, US
Melvin Stene - Pocatello ID, US
Brian Kauffmann - Pocatello ID, US

G01R023/175

324/076540

A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal, A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block. The delay lock loop circuit is capable of handling a wide range of clock frequencies and a step increase or decrease in the clock frequency.